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d645427057
In my "build everything" tree, changing migration/vmstate.h triggers a recompile of some 2700 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h). hw/hw.h supposedly includes it for convenience. Several other headers include it just to get VMStateDescription. The previous commit made that unnecessary. Include migration/vmstate.h only where it's still needed. Touching it now recompiles only some 1600 objects. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190812052359.30071-16-armbru@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
168 lines
4.7 KiB
C
168 lines
4.7 KiB
C
/*
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* ASPEED XDMA Controller
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* Eddie James <eajames@linux.ibm.com>
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*
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* Copyright (C) 2019 IBM Corp
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* SPDX-License-Identifer: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "hw/irq.h"
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#include "hw/misc/aspeed_xdma.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "trace.h"
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#define XDMA_BMC_CMDQ_ADDR 0x10
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#define XDMA_BMC_CMDQ_ENDP 0x14
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#define XDMA_BMC_CMDQ_WRP 0x18
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#define XDMA_BMC_CMDQ_W_MASK 0x0003FFFF
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#define XDMA_BMC_CMDQ_RDP 0x1C
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#define XDMA_BMC_CMDQ_RDP_MAGIC 0xEE882266
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#define XDMA_IRQ_ENG_CTRL 0x20
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#define XDMA_IRQ_ENG_CTRL_US_COMP BIT(4)
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#define XDMA_IRQ_ENG_CTRL_DS_COMP BIT(5)
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#define XDMA_IRQ_ENG_CTRL_W_MASK 0xBFEFF07F
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#define XDMA_IRQ_ENG_STAT 0x24
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#define XDMA_IRQ_ENG_STAT_US_COMP BIT(4)
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#define XDMA_IRQ_ENG_STAT_DS_COMP BIT(5)
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#define XDMA_IRQ_ENG_STAT_RESET 0xF8000000
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#define XDMA_MEM_SIZE 0x1000
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#define TO_REG(addr) ((addr) / sizeof(uint32_t))
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static uint64_t aspeed_xdma_read(void *opaque, hwaddr addr, unsigned int size)
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{
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uint32_t val = 0;
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AspeedXDMAState *xdma = opaque;
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if (addr < ASPEED_XDMA_REG_SIZE) {
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val = xdma->regs[TO_REG(addr)];
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}
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return (uint64_t)val;
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}
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static void aspeed_xdma_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int size)
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{
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unsigned int idx;
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uint32_t val32 = (uint32_t)val;
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AspeedXDMAState *xdma = opaque;
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if (addr >= ASPEED_XDMA_REG_SIZE) {
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return;
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}
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switch (addr) {
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case XDMA_BMC_CMDQ_ENDP:
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xdma->regs[TO_REG(addr)] = val32 & XDMA_BMC_CMDQ_W_MASK;
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break;
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case XDMA_BMC_CMDQ_WRP:
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idx = TO_REG(addr);
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xdma->regs[idx] = val32 & XDMA_BMC_CMDQ_W_MASK;
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xdma->regs[TO_REG(XDMA_BMC_CMDQ_RDP)] = xdma->regs[idx];
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trace_aspeed_xdma_write(addr, val);
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if (xdma->bmc_cmdq_readp_set) {
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xdma->bmc_cmdq_readp_set = 0;
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} else {
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xdma->regs[TO_REG(XDMA_IRQ_ENG_STAT)] |=
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XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP;
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if (xdma->regs[TO_REG(XDMA_IRQ_ENG_CTRL)] &
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(XDMA_IRQ_ENG_CTRL_US_COMP | XDMA_IRQ_ENG_CTRL_DS_COMP))
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qemu_irq_raise(xdma->irq);
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}
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break;
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case XDMA_BMC_CMDQ_RDP:
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trace_aspeed_xdma_write(addr, val);
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if (val32 == XDMA_BMC_CMDQ_RDP_MAGIC) {
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xdma->bmc_cmdq_readp_set = 1;
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}
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break;
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case XDMA_IRQ_ENG_CTRL:
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xdma->regs[TO_REG(addr)] = val32 & XDMA_IRQ_ENG_CTRL_W_MASK;
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break;
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case XDMA_IRQ_ENG_STAT:
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trace_aspeed_xdma_write(addr, val);
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idx = TO_REG(addr);
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if (val32 & (XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP)) {
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xdma->regs[idx] &=
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~(XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP);
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qemu_irq_lower(xdma->irq);
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}
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break;
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default:
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xdma->regs[TO_REG(addr)] = val32;
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break;
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}
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}
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static const MemoryRegionOps aspeed_xdma_ops = {
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.read = aspeed_xdma_read,
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.write = aspeed_xdma_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static void aspeed_xdma_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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AspeedXDMAState *xdma = ASPEED_XDMA(dev);
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sysbus_init_irq(sbd, &xdma->irq);
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memory_region_init_io(&xdma->iomem, OBJECT(xdma), &aspeed_xdma_ops, xdma,
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TYPE_ASPEED_XDMA, XDMA_MEM_SIZE);
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sysbus_init_mmio(sbd, &xdma->iomem);
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}
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static void aspeed_xdma_reset(DeviceState *dev)
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{
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AspeedXDMAState *xdma = ASPEED_XDMA(dev);
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xdma->bmc_cmdq_readp_set = 0;
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memset(xdma->regs, 0, ASPEED_XDMA_REG_SIZE);
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xdma->regs[TO_REG(XDMA_IRQ_ENG_STAT)] = XDMA_IRQ_ENG_STAT_RESET;
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qemu_irq_lower(xdma->irq);
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}
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static const VMStateDescription aspeed_xdma_vmstate = {
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.name = TYPE_ASPEED_XDMA,
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.version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, AspeedXDMAState, ASPEED_XDMA_NUM_REGS),
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VMSTATE_END_OF_LIST(),
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},
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};
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static void aspeed_xdma_class_init(ObjectClass *classp, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(classp);
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dc->realize = aspeed_xdma_realize;
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dc->reset = aspeed_xdma_reset;
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dc->vmsd = &aspeed_xdma_vmstate;
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}
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static const TypeInfo aspeed_xdma_info = {
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.name = TYPE_ASPEED_XDMA,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AspeedXDMAState),
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.class_init = aspeed_xdma_class_init,
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};
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static void aspeed_xdma_register_type(void)
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{
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type_register_static(&aspeed_xdma_info);
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}
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type_init(aspeed_xdma_register_type);
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