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2df7566445
This implement exclusive loads/stores for aarch64 along the lines of arm32 and ppc implementations. The exclusive load remembers the address and loaded value. The exclusive store throws an an exception which uses those values to check for equality in a proper exclusive region. This is not actually the architecture mandated semantics (for either AArch32 or AArch64) but it is close enough for typical guest code sequences to work correctly, and saves us from having to monitor all guest stores. It's fairly easy to come up with test cases where we don't behave like hardware - we don't for example model cache line behaviour. However in the common patterns this works, and the existing 32 bit ARM exclusive access implementation has the same limitations. AArch64 also implements new acquire/release loads/stores (which may be either exclusive or non-exclusive). These imposes extra ordering constraints on memory operations (ie they act as if they have an implicit barrier built into them). As TCG is single-threaded all our barriers are no-ops, so these just behave like normal loads and stores. Signed-off-by: Michael Matz <matz@suse.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> |
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| .. | ||
| aarch64 | ||
| alpha | ||
| arm | ||
| cris | ||
| i386 | ||
| m68k | ||
| microblaze | ||
| mips | ||
| mips64 | ||
| openrisc | ||
| ppc | ||
| s390x | ||
| sh4 | ||
| sparc | ||
| sparc64 | ||
| unicore32 | ||
| x86_64 | ||
| cpu-uname.c | ||
| cpu-uname.h | ||
| elfload.c | ||
| errno_defs.h | ||
| flat.h | ||
| flatload.c | ||
| ioctls.h | ||
| linux_loop.h | ||
| linuxload.c | ||
| m68k-sim.c | ||
| main.c | ||
| Makefile.objs | ||
| mmap.c | ||
| qemu.h | ||
| signal.c | ||
| socket.h | ||
| strace.c | ||
| strace.list | ||
| syscall_defs.h | ||
| syscall_types.h | ||
| syscall.c | ||
| target_flat.h | ||
| uaccess.c | ||
| vm86.c | ||