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c53be33474
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1594 c046a42c-6fe2-441c-8c8c-71466251a162
1292 lines
17 KiB
C
1292 lines
17 KiB
C
/*
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* PowerPC emulation micro-operations for qemu.
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*
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* Copyright (c) 2003-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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//#define DEBUG_OP
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#include "config.h"
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#include "exec.h"
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#define regs (env)
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#define Ts0 (int32_t)T0
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#define Ts1 (int32_t)T1
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#define Ts2 (int32_t)T2
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#define FT0 (env->ft0)
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#define FT1 (env->ft1)
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#define FT2 (env->ft2)
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#define PPC_OP(name) void glue(op_, name)(void)
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#define REG 0
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#include "op_template.h"
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#define REG 1
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#include "op_template.h"
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#define REG 2
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#include "op_template.h"
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#define REG 3
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#include "op_template.h"
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#define REG 4
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#include "op_template.h"
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#define REG 5
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#include "op_template.h"
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#define REG 6
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#include "op_template.h"
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#define REG 7
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#include "op_template.h"
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#define REG 8
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#include "op_template.h"
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#define REG 9
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#include "op_template.h"
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#define REG 10
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#include "op_template.h"
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#define REG 11
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#include "op_template.h"
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#define REG 12
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#include "op_template.h"
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#define REG 13
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#include "op_template.h"
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#define REG 14
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#include "op_template.h"
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#define REG 15
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#include "op_template.h"
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#define REG 16
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#include "op_template.h"
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#define REG 17
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#include "op_template.h"
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#define REG 18
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#include "op_template.h"
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#define REG 19
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#include "op_template.h"
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#define REG 20
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#include "op_template.h"
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#define REG 21
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#include "op_template.h"
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#define REG 22
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#include "op_template.h"
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#define REG 23
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#include "op_template.h"
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#define REG 24
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#include "op_template.h"
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#define REG 25
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#include "op_template.h"
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#define REG 26
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#include "op_template.h"
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#define REG 27
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#include "op_template.h"
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#define REG 28
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#include "op_template.h"
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#define REG 29
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#include "op_template.h"
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#define REG 30
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#include "op_template.h"
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#define REG 31
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#include "op_template.h"
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/* PowerPC state maintenance operations */
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/* set_Rc0 */
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PPC_OP(set_Rc0)
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{
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uint32_t tmp;
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if (Ts0 < 0) {
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tmp = 0x08;
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} else if (Ts0 > 0) {
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tmp = 0x04;
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} else {
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tmp = 0x02;
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}
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tmp |= xer_ov;
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env->crf[0] = tmp;
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RETURN();
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}
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/* reset_Rc0 */
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PPC_OP(reset_Rc0)
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{
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env->crf[0] = 0x02 | xer_ov;
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RETURN();
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}
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/* set_Rc0_1 */
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PPC_OP(set_Rc0_1)
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{
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env->crf[0] = 0x04 | xer_ov;
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RETURN();
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}
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/* Set Rc1 (for floating point arithmetic) */
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PPC_OP(set_Rc1)
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{
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env->crf[1] = regs->fpscr[7];
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RETURN();
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}
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/* Constants load */
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PPC_OP(set_T0)
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{
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T0 = PARAM(1);
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RETURN();
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}
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PPC_OP(set_T1)
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{
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T1 = PARAM(1);
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RETURN();
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}
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PPC_OP(set_T2)
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{
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T2 = PARAM(1);
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RETURN();
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}
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/* Generate exceptions */
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PPC_OP(raise_exception_err)
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{
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do_raise_exception_err(PARAM(1), PARAM(2));
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}
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PPC_OP(raise_exception)
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{
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do_raise_exception(PARAM(1));
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}
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PPC_OP(update_nip)
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{
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env->nip = PARAM(1);
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}
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/* Segment registers load and store with immediate index */
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PPC_OP(load_srin)
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{
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T0 = regs->sr[T1 >> 28];
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RETURN();
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}
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PPC_OP(store_srin)
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{
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do_store_sr(env, ((uint32_t)T1 >> 28), T0);
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RETURN();
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}
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PPC_OP(load_sdr1)
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{
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T0 = regs->sdr1;
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RETURN();
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}
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PPC_OP(store_sdr1)
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{
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do_store_sdr1(env, T0);
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RETURN();
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}
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PPC_OP(exit_tb)
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{
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EXIT_TB();
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}
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/* Load/store special registers */
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PPC_OP(load_cr)
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{
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T0 = do_load_cr(env);
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RETURN();
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}
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PPC_OP(store_cr)
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{
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do_store_cr(env, T0, PARAM(1));
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RETURN();
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}
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PPC_OP(load_xer_cr)
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{
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T0 = (xer_so << 3) | (xer_ov << 2) | (xer_ca << 1);
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RETURN();
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}
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PPC_OP(clear_xer_cr)
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{
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xer_so = 0;
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xer_ov = 0;
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xer_ca = 0;
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RETURN();
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}
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PPC_OP(load_xer_bc)
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{
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T1 = xer_bc;
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RETURN();
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}
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PPC_OP(load_xer)
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{
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T0 = do_load_xer(env);
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RETURN();
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}
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PPC_OP(store_xer)
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{
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do_store_xer(env, T0);
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RETURN();
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}
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PPC_OP(load_msr)
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{
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T0 = do_load_msr(env);
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RETURN();
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}
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PPC_OP(store_msr)
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{
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do_store_msr(env, T0);
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RETURN();
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}
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/* SPR */
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PPC_OP(load_spr)
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{
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T0 = regs->spr[PARAM(1)];
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RETURN();
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}
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PPC_OP(store_spr)
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{
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regs->spr[PARAM(1)] = T0;
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RETURN();
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}
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PPC_OP(load_lr)
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{
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T0 = regs->lr;
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RETURN();
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}
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PPC_OP(store_lr)
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{
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regs->lr = T0;
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RETURN();
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}
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PPC_OP(load_ctr)
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{
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T0 = regs->ctr;
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RETURN();
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}
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PPC_OP(store_ctr)
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{
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regs->ctr = T0;
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RETURN();
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}
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PPC_OP(load_tbl)
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{
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T0 = cpu_ppc_load_tbl(regs);
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RETURN();
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}
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PPC_OP(load_tbu)
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{
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T0 = cpu_ppc_load_tbu(regs);
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RETURN();
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}
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PPC_OP(store_tbl)
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{
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cpu_ppc_store_tbl(regs, T0);
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RETURN();
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}
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PPC_OP(store_tbu)
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{
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cpu_ppc_store_tbu(regs, T0);
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RETURN();
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}
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PPC_OP(load_decr)
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{
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T0 = cpu_ppc_load_decr(regs);
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}
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PPC_OP(store_decr)
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{
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cpu_ppc_store_decr(regs, T0);
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RETURN();
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}
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PPC_OP(load_ibat)
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{
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T0 = regs->IBAT[PARAM(1)][PARAM(2)];
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}
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void op_store_ibatu (void)
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{
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do_store_ibatu(env, PARAM1, T0);
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RETURN();
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}
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void op_store_ibatl (void)
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{
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#if 1
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env->IBAT[1][PARAM1] = T0;
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#else
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do_store_ibatl(env, PARAM1, T0);
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#endif
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RETURN();
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}
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PPC_OP(load_dbat)
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{
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T0 = regs->DBAT[PARAM(1)][PARAM(2)];
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}
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void op_store_dbatu (void)
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{
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do_store_dbatu(env, PARAM1, T0);
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RETURN();
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}
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void op_store_dbatl (void)
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{
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#if 1
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env->DBAT[1][PARAM1] = T0;
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#else
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do_store_dbatl(env, PARAM1, T0);
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#endif
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RETURN();
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}
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/* FPSCR */
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PPC_OP(load_fpscr)
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{
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FT0 = do_load_fpscr(env);
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RETURN();
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}
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PPC_OP(store_fpscr)
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{
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do_store_fpscr(env, FT0, PARAM1);
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RETURN();
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}
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PPC_OP(reset_scrfx)
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{
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regs->fpscr[7] &= ~0x8;
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RETURN();
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}
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/* crf operations */
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PPC_OP(getbit_T0)
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{
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T0 = (T0 >> PARAM(1)) & 1;
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RETURN();
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}
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PPC_OP(getbit_T1)
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{
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T1 = (T1 >> PARAM(1)) & 1;
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RETURN();
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}
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PPC_OP(setcrfbit)
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{
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T1 = (T1 & PARAM(1)) | (T0 << PARAM(2));
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RETURN();
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}
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/* Branch */
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#define EIP regs->nip
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PPC_OP(setlr)
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{
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regs->lr = PARAM1;
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}
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PPC_OP(goto_tb0)
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{
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GOTO_TB(op_goto_tb0, PARAM1, 0);
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}
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PPC_OP(goto_tb1)
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{
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GOTO_TB(op_goto_tb1, PARAM1, 1);
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}
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PPC_OP(b_T1)
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{
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regs->nip = T1 & ~3;
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}
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PPC_OP(jz_T0)
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{
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if (!T0)
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GOTO_LABEL_PARAM(1);
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RETURN();
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}
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PPC_OP(btest_T1)
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{
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if (T0) {
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regs->nip = T1 & ~3;
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} else {
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regs->nip = PARAM1;
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}
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RETURN();
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}
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PPC_OP(movl_T1_ctr)
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{
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T1 = regs->ctr;
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}
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PPC_OP(movl_T1_lr)
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{
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T1 = regs->lr;
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}
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/* tests with result in T0 */
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PPC_OP(test_ctr)
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{
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T0 = regs->ctr;
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}
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PPC_OP(test_ctr_true)
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{
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T0 = (regs->ctr != 0 && (T0 & PARAM(1)) != 0);
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}
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PPC_OP(test_ctr_false)
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{
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T0 = (regs->ctr != 0 && (T0 & PARAM(1)) == 0);
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}
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PPC_OP(test_ctrz)
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{
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T0 = (regs->ctr == 0);
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}
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PPC_OP(test_ctrz_true)
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{
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T0 = (regs->ctr == 0 && (T0 & PARAM(1)) != 0);
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}
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PPC_OP(test_ctrz_false)
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{
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T0 = (regs->ctr == 0 && (T0 & PARAM(1)) == 0);
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}
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PPC_OP(test_true)
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{
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T0 = (T0 & PARAM(1));
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}
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PPC_OP(test_false)
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{
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T0 = ((T0 & PARAM(1)) == 0);
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}
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/* CTR maintenance */
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PPC_OP(dec_ctr)
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{
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regs->ctr--;
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RETURN();
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}
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/*** Integer arithmetic ***/
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/* add */
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PPC_OP(add)
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{
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T0 += T1;
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RETURN();
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}
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void do_addo (void);
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void op_addo (void)
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{
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do_addo();
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RETURN();
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}
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/* add carrying */
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PPC_OP(addc)
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{
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T2 = T0;
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T0 += T1;
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if (T0 < T2) {
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xer_ca = 1;
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} else {
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xer_ca = 0;
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}
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RETURN();
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}
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void do_addco (void);
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void op_addco (void)
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{
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do_addco();
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RETURN();
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}
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/* add extended */
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void do_adde (void);
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void op_adde (void)
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{
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do_adde();
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}
|
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void do_addeo (void);
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PPC_OP(addeo)
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{
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do_addeo();
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RETURN();
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}
|
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/* add immediate */
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PPC_OP(addi)
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{
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T0 += PARAM(1);
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RETURN();
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}
|
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/* add immediate carrying */
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PPC_OP(addic)
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{
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T1 = T0;
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T0 += PARAM(1);
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if (T0 < T1) {
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xer_ca = 1;
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} else {
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xer_ca = 0;
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}
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RETURN();
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}
|
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|
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/* add to minus one extended */
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PPC_OP(addme)
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{
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T1 = T0;
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T0 += xer_ca + (-1);
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if (T1 != 0)
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xer_ca = 1;
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RETURN();
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}
|
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|
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void do_addmeo (void);
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void op_addmeo (void)
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{
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do_addmeo();
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RETURN();
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}
|
|
|
|
/* add to zero extended */
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PPC_OP(addze)
|
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{
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T1 = T0;
|
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T0 += xer_ca;
|
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if (T0 < T1) {
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xer_ca = 1;
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} else {
|
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xer_ca = 0;
|
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}
|
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RETURN();
|
|
}
|
|
|
|
void do_addzeo (void);
|
|
void op_addzeo (void)
|
|
{
|
|
do_addzeo();
|
|
RETURN();
|
|
}
|
|
|
|
/* divide word */
|
|
PPC_OP(divw)
|
|
{
|
|
if ((Ts0 == INT32_MIN && Ts1 == -1) || Ts1 == 0) {
|
|
T0 = (int32_t)((-1) * (T0 >> 31));
|
|
} else {
|
|
T0 = (Ts0 / Ts1);
|
|
}
|
|
RETURN();
|
|
}
|
|
|
|
void do_divwo (void);
|
|
void op_divwo (void)
|
|
{
|
|
do_divwo();
|
|
RETURN();
|
|
}
|
|
|
|
/* divide word unsigned */
|
|
PPC_OP(divwu)
|
|
{
|
|
if (T1 == 0) {
|
|
T0 = 0;
|
|
} else {
|
|
T0 /= T1;
|
|
}
|
|
RETURN();
|
|
}
|
|
|
|
void do_divwuo (void);
|
|
void op_divwuo (void)
|
|
{
|
|
do_divwuo();
|
|
RETURN();
|
|
}
|
|
|
|
/* multiply high word */
|
|
PPC_OP(mulhw)
|
|
{
|
|
T0 = ((int64_t)Ts0 * (int64_t)Ts1) >> 32;
|
|
RETURN();
|
|
}
|
|
|
|
/* multiply high word unsigned */
|
|
PPC_OP(mulhwu)
|
|
{
|
|
T0 = ((uint64_t)T0 * (uint64_t)T1) >> 32;
|
|
RETURN();
|
|
}
|
|
|
|
/* multiply low immediate */
|
|
PPC_OP(mulli)
|
|
{
|
|
T0 = (Ts0 * SPARAM(1));
|
|
RETURN();
|
|
}
|
|
|
|
/* multiply low word */
|
|
PPC_OP(mullw)
|
|
{
|
|
T0 *= T1;
|
|
RETURN();
|
|
}
|
|
|
|
void do_mullwo (void);
|
|
void op_mullwo (void)
|
|
{
|
|
do_mullwo();
|
|
RETURN();
|
|
}
|
|
|
|
/* negate */
|
|
PPC_OP(neg)
|
|
{
|
|
if (T0 != 0x80000000) {
|
|
T0 = -Ts0;
|
|
}
|
|
RETURN();
|
|
}
|
|
|
|
void do_nego (void);
|
|
void op_nego (void)
|
|
{
|
|
do_nego();
|
|
RETURN();
|
|
}
|
|
|
|
/* substract from */
|
|
PPC_OP(subf)
|
|
{
|
|
T0 = T1 - T0;
|
|
RETURN();
|
|
}
|
|
|
|
void do_subfo (void);
|
|
void op_subfo (void)
|
|
{
|
|
do_subfo();
|
|
RETURN();
|
|
}
|
|
|
|
/* substract from carrying */
|
|
PPC_OP(subfc)
|
|
{
|
|
T0 = T1 - T0;
|
|
if (T0 <= T1) {
|
|
xer_ca = 1;
|
|
} else {
|
|
xer_ca = 0;
|
|
}
|
|
RETURN();
|
|
}
|
|
|
|
void do_subfco (void);
|
|
void op_subfco (void)
|
|
{
|
|
do_subfco();
|
|
RETURN();
|
|
}
|
|
|
|
/* substract from extended */
|
|
void do_subfe (void);
|
|
void op_subfe (void)
|
|
{
|
|
do_subfe();
|
|
RETURN();
|
|
}
|
|
|
|
void do_subfeo (void);
|
|
PPC_OP(subfeo)
|
|
{
|
|
do_subfeo();
|
|
RETURN();
|
|
}
|
|
|
|
/* substract from immediate carrying */
|
|
PPC_OP(subfic)
|
|
{
|
|
T0 = PARAM(1) + ~T0 + 1;
|
|
if (T0 <= PARAM(1)) {
|
|
xer_ca = 1;
|
|
} else {
|
|
xer_ca = 0;
|
|
}
|
|
RETURN();
|
|
}
|
|
|
|
/* substract from minus one extended */
|
|
PPC_OP(subfme)
|
|
{
|
|
T0 = ~T0 + xer_ca - 1;
|
|
|
|
if (T0 != -1)
|
|
xer_ca = 1;
|
|
RETURN();
|
|
}
|
|
|
|
void do_subfmeo (void);
|
|
void op_subfmeo (void)
|
|
{
|
|
do_subfmeo();
|
|
RETURN();
|
|
}
|
|
|
|
/* substract from zero extended */
|
|
PPC_OP(subfze)
|
|
{
|
|
T1 = ~T0;
|
|
T0 = T1 + xer_ca;
|
|
if (T0 < T1) {
|
|
xer_ca = 1;
|
|
} else {
|
|
xer_ca = 0;
|
|
}
|
|
RETURN();
|
|
}
|
|
|
|
void do_subfzeo (void);
|
|
void op_subfzeo (void)
|
|
{
|
|
do_subfzeo();
|
|
RETURN();
|
|
}
|
|
|
|
/*** Integer comparison ***/
|
|
/* compare */
|
|
PPC_OP(cmp)
|
|
{
|
|
if (Ts0 < Ts1) {
|
|
T0 = 0x08;
|
|
} else if (Ts0 > Ts1) {
|
|
T0 = 0x04;
|
|
} else {
|
|
T0 = 0x02;
|
|
}
|
|
RETURN();
|
|
}
|
|
|
|
/* compare immediate */
|
|
PPC_OP(cmpi)
|
|
{
|
|
if (Ts0 < SPARAM(1)) {
|
|
T0 = 0x08;
|
|
} else if (Ts0 > SPARAM(1)) {
|
|
T0 = 0x04;
|
|
} else {
|
|
T0 = 0x02;
|
|
}
|
|
RETURN();
|
|
}
|
|
|
|
/* compare logical */
|
|
PPC_OP(cmpl)
|
|
{
|
|
if (T0 < T1) {
|
|
T0 = 0x08;
|
|
} else if (T0 > T1) {
|
|
T0 = 0x04;
|
|
} else {
|
|
T0 = 0x02;
|
|
}
|
|
RETURN();
|
|
}
|
|
|
|
/* compare logical immediate */
|
|
PPC_OP(cmpli)
|
|
{
|
|
if (T0 < PARAM(1)) {
|
|
T0 = 0x08;
|
|
} else if (T0 > PARAM(1)) {
|
|
T0 = 0x04;
|
|
} else {
|
|
T0 = 0x02;
|
|
}
|
|
RETURN();
|
|
}
|
|
|
|
/*** Integer logical ***/
|
|
/* and */
|
|
PPC_OP(and)
|
|
{
|
|
T0 &= T1;
|
|
RETURN();
|
|
}
|
|
|
|
/* andc */
|
|
PPC_OP(andc)
|
|
{
|
|
T0 &= ~T1;
|
|
RETURN();
|
|
}
|
|
|
|
/* andi. */
|
|
PPC_OP(andi_)
|
|
{
|
|
T0 &= PARAM(1);
|
|
RETURN();
|
|
}
|
|
|
|
/* count leading zero */
|
|
PPC_OP(cntlzw)
|
|
{
|
|
T1 = T0;
|
|
for (T0 = 32; T1 > 0; T0--)
|
|
T1 = T1 >> 1;
|
|
RETURN();
|
|
}
|
|
|
|
/* eqv */
|
|
PPC_OP(eqv)
|
|
{
|
|
T0 = ~(T0 ^ T1);
|
|
RETURN();
|
|
}
|
|
|
|
/* extend sign byte */
|
|
PPC_OP(extsb)
|
|
{
|
|
T0 = (int32_t)((int8_t)(Ts0));
|
|
RETURN();
|
|
}
|
|
|
|
/* extend sign half word */
|
|
PPC_OP(extsh)
|
|
{
|
|
T0 = (int32_t)((int16_t)(Ts0));
|
|
RETURN();
|
|
}
|
|
|
|
/* nand */
|
|
PPC_OP(nand)
|
|
{
|
|
T0 = ~(T0 & T1);
|
|
RETURN();
|
|
}
|
|
|
|
/* nor */
|
|
PPC_OP(nor)
|
|
{
|
|
T0 = ~(T0 | T1);
|
|
RETURN();
|
|
}
|
|
|
|
/* or */
|
|
PPC_OP(or)
|
|
{
|
|
T0 |= T1;
|
|
RETURN();
|
|
}
|
|
|
|
/* orc */
|
|
PPC_OP(orc)
|
|
{
|
|
T0 |= ~T1;
|
|
RETURN();
|
|
}
|
|
|
|
/* ori */
|
|
PPC_OP(ori)
|
|
{
|
|
T0 |= PARAM(1);
|
|
RETURN();
|
|
}
|
|
|
|
/* xor */
|
|
PPC_OP(xor)
|
|
{
|
|
T0 ^= T1;
|
|
RETURN();
|
|
}
|
|
|
|
/* xori */
|
|
PPC_OP(xori)
|
|
{
|
|
T0 ^= PARAM(1);
|
|
RETURN();
|
|
}
|
|
|
|
/*** Integer rotate ***/
|
|
/* rotate left word immediate then mask insert */
|
|
PPC_OP(rlwimi)
|
|
{
|
|
T0 = (rotl(T0, PARAM(1)) & PARAM(2)) | (T1 & PARAM(3));
|
|
RETURN();
|
|
}
|
|
|
|
/* rotate left immediate then and with mask insert */
|
|
PPC_OP(rotlwi)
|
|
{
|
|
T0 = rotl(T0, PARAM(1));
|
|
RETURN();
|
|
}
|
|
|
|
PPC_OP(slwi)
|
|
{
|
|
T0 = T0 << PARAM(1);
|
|
RETURN();
|
|
}
|
|
|
|
PPC_OP(srwi)
|
|
{
|
|
T0 = T0 >> PARAM(1);
|
|
RETURN();
|
|
}
|
|
|
|
/* rotate left word then and with mask insert */
|
|
PPC_OP(rlwinm)
|
|
{
|
|
T0 = rotl(T0, PARAM(1)) & PARAM(2);
|
|
RETURN();
|
|
}
|
|
|
|
PPC_OP(rotl)
|
|
{
|
|
T0 = rotl(T0, T1);
|
|
RETURN();
|
|
}
|
|
|
|
PPC_OP(rlwnm)
|
|
{
|
|
T0 = rotl(T0, T1) & PARAM(1);
|
|
RETURN();
|
|
}
|
|
|
|
/*** Integer shift ***/
|
|
/* shift left word */
|
|
PPC_OP(slw)
|
|
{
|
|
if (T1 & 0x20) {
|
|
T0 = 0;
|
|
} else {
|
|
T0 = T0 << T1;
|
|
}
|
|
RETURN();
|
|
}
|
|
|
|
/* shift right algebraic word */
|
|
void op_sraw (void)
|
|
{
|
|
do_sraw();
|
|
RETURN();
|
|
}
|
|
|
|
/* shift right algebraic word immediate */
|
|
PPC_OP(srawi)
|
|
{
|
|
T1 = T0;
|
|
T0 = (Ts0 >> PARAM(1));
|
|
if (Ts1 < 0 && (Ts1 & PARAM(2)) != 0) {
|
|
xer_ca = 1;
|
|
} else {
|
|
xer_ca = 0;
|
|
}
|
|
RETURN();
|
|
}
|
|
|
|
/* shift right word */
|
|
PPC_OP(srw)
|
|
{
|
|
if (T1 & 0x20) {
|
|
T0 = 0;
|
|
} else {
|
|
T0 = T0 >> T1;
|
|
}
|
|
RETURN();
|
|
}
|
|
|
|
/*** Floating-Point arithmetic ***/
|
|
/* fadd - fadd. */
|
|
PPC_OP(fadd)
|
|
{
|
|
FT0 += FT1;
|
|
RETURN();
|
|
}
|
|
|
|
/* fsub - fsub. */
|
|
PPC_OP(fsub)
|
|
{
|
|
FT0 -= FT1;
|
|
RETURN();
|
|
}
|
|
|
|
/* fmul - fmul. */
|
|
PPC_OP(fmul)
|
|
{
|
|
FT0 *= FT1;
|
|
RETURN();
|
|
}
|
|
|
|
/* fdiv - fdiv. */
|
|
PPC_OP(fdiv)
|
|
{
|
|
FT0 = float64_div(FT0, FT1, &env->fp_status);
|
|
RETURN();
|
|
}
|
|
|
|
/* fsqrt - fsqrt. */
|
|
PPC_OP(fsqrt)
|
|
{
|
|
do_fsqrt();
|
|
RETURN();
|
|
}
|
|
|
|
/* fres - fres. */
|
|
PPC_OP(fres)
|
|
{
|
|
do_fres();
|
|
RETURN();
|
|
}
|
|
|
|
/* frsqrte - frsqrte. */
|
|
PPC_OP(frsqrte)
|
|
{
|
|
do_frsqrte();
|
|
RETURN();
|
|
}
|
|
|
|
/* fsel - fsel. */
|
|
PPC_OP(fsel)
|
|
{
|
|
do_fsel();
|
|
RETURN();
|
|
}
|
|
|
|
/*** Floating-Point multiply-and-add ***/
|
|
/* fmadd - fmadd. */
|
|
PPC_OP(fmadd)
|
|
{
|
|
FT0 = (FT0 * FT1) + FT2;
|
|
RETURN();
|
|
}
|
|
|
|
/* fmsub - fmsub. */
|
|
PPC_OP(fmsub)
|
|
{
|
|
FT0 = (FT0 * FT1) - FT2;
|
|
RETURN();
|
|
}
|
|
|
|
/* fnmadd - fnmadd. - fnmadds - fnmadds. */
|
|
PPC_OP(fnmadd)
|
|
{
|
|
do_fnmadd();
|
|
RETURN();
|
|
}
|
|
|
|
/* fnmsub - fnmsub. */
|
|
PPC_OP(fnmsub)
|
|
{
|
|
do_fnmsub();
|
|
RETURN();
|
|
}
|
|
|
|
/*** Floating-Point round & convert ***/
|
|
/* frsp - frsp. */
|
|
PPC_OP(frsp)
|
|
{
|
|
FT0 = (float)FT0;
|
|
RETURN();
|
|
}
|
|
|
|
/* fctiw - fctiw. */
|
|
PPC_OP(fctiw)
|
|
{
|
|
do_fctiw();
|
|
RETURN();
|
|
}
|
|
|
|
/* fctiwz - fctiwz. */
|
|
PPC_OP(fctiwz)
|
|
{
|
|
do_fctiwz();
|
|
RETURN();
|
|
}
|
|
|
|
|
|
/*** Floating-Point compare ***/
|
|
/* fcmpu */
|
|
PPC_OP(fcmpu)
|
|
{
|
|
do_fcmpu();
|
|
RETURN();
|
|
}
|
|
|
|
/* fcmpo */
|
|
PPC_OP(fcmpo)
|
|
{
|
|
do_fcmpo();
|
|
RETURN();
|
|
}
|
|
|
|
/*** Floating-point move ***/
|
|
/* fabs */
|
|
PPC_OP(fabs)
|
|
{
|
|
FT0 = float64_abs(FT0);
|
|
RETURN();
|
|
}
|
|
|
|
/* fnabs */
|
|
PPC_OP(fnabs)
|
|
{
|
|
FT0 = float64_abs(FT0);
|
|
FT0 = float64_chs(FT0);
|
|
RETURN();
|
|
}
|
|
|
|
/* fneg */
|
|
PPC_OP(fneg)
|
|
{
|
|
FT0 = float64_chs(FT0);
|
|
RETURN();
|
|
}
|
|
|
|
/* Load and store */
|
|
#define MEMSUFFIX _raw
|
|
#include "op_mem.h"
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
#define MEMSUFFIX _user
|
|
#include "op_mem.h"
|
|
|
|
#define MEMSUFFIX _kernel
|
|
#include "op_mem.h"
|
|
#endif
|
|
|
|
/* Special op to check and maybe clear reservation */
|
|
PPC_OP(check_reservation)
|
|
{
|
|
if ((uint32_t)env->reserve == (uint32_t)(T0 & ~0x00000003))
|
|
env->reserve = -1;
|
|
RETURN();
|
|
}
|
|
|
|
/* Return from interrupt */
|
|
void do_rfi (void);
|
|
void op_rfi (void)
|
|
{
|
|
do_rfi();
|
|
RETURN();
|
|
}
|
|
|
|
/* Trap word */
|
|
void do_tw (uint32_t cmp, int flags);
|
|
void op_tw (void)
|
|
{
|
|
do_tw(T1, PARAM(1));
|
|
RETURN();
|
|
}
|
|
|
|
void op_twi (void)
|
|
{
|
|
do_tw(PARAM(1), PARAM(2));
|
|
RETURN();
|
|
}
|
|
|
|
/* Instruction cache block invalidate */
|
|
PPC_OP(icbi)
|
|
{
|
|
do_icbi();
|
|
RETURN();
|
|
}
|
|
|
|
/* tlbia */
|
|
PPC_OP(tlbia)
|
|
{
|
|
do_tlbia();
|
|
RETURN();
|
|
}
|
|
|
|
/* tlbie */
|
|
PPC_OP(tlbie)
|
|
{
|
|
do_tlbie();
|
|
RETURN();
|
|
}
|
|
|
|
void op_store_pir (void)
|
|
{
|
|
env->spr[SPR_PIR] = T0 & 0x0000000FUL;
|
|
RETURN();
|
|
}
|