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There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023122913.19561-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
83 lines
3.3 KiB
Plaintext
83 lines
3.3 KiB
Plaintext
# AArch32 VFP instruction descriptions (unconditional insns)
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#
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# Copyright (c) 2019 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2.1 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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# Encodings for the unconditional VFP instructions are here:
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# generally anything matching A32
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# 1111 1110 .... .... .... 101. ...0 ....
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# and T32
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# 1111 110. .... .... .... 101. .... ....
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# 1111 1110 .... .... .... 101. .... ....
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# (but those patterns might also cover some Neon instructions,
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# which do not live in this file.)
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# VFP registers have an odd encoding with a four-bit field
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# and a one-bit field which are assembled in different orders
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# depending on whether the register is double or single precision.
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# Each individual instruction function must do the checks for
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# "double register selected but CPU does not have double support"
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# and "double register number has bit 4 set but CPU does not
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# support D16-D31" (which should UNDEF).
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%vm_dp 5:1 0:4
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%vm_sp 0:4 5:1
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%vn_dp 7:1 16:4
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%vn_sp 16:4 7:1
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%vd_dp 22:1 12:4
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%vd_sp 12:4 22:1
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@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp
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@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp
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VSEL 1111 1110 0. cc:2 .... .... 1001 .0.0 .... \
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vm=%vm_sp vn=%vn_sp vd=%vd_sp sz=1
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VSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \
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vm=%vm_sp vn=%vn_sp vd=%vd_sp sz=2
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VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \
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vm=%vm_dp vn=%vn_dp vd=%vd_dp sz=3
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VMAXNM_hp 1111 1110 1.00 .... .... 1001 .0.0 .... @vfp_dnm_s
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VMINNM_hp 1111 1110 1.00 .... .... 1001 .1.0 .... @vfp_dnm_s
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VMAXNM_sp 1111 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s
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VMINNM_sp 1111 1110 1.00 .... .... 1010 .1.0 .... @vfp_dnm_s
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VMAXNM_dp 1111 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d
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VMINNM_dp 1111 1110 1.00 .... .... 1011 .1.0 .... @vfp_dnm_d
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VRINT 1111 1110 1.11 10 rm:2 .... 1001 01.0 .... \
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vm=%vm_sp vd=%vd_sp sz=1
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VRINT 1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \
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vm=%vm_sp vd=%vd_sp sz=2
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VRINT 1111 1110 1.11 10 rm:2 .... 1011 01.0 .... \
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vm=%vm_dp vd=%vd_dp sz=3
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# VCVT float to int with specified rounding mode; Vd is always single-precision
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VCVT 1111 1110 1.11 11 rm:2 .... 1001 op:1 1.0 .... \
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vm=%vm_sp vd=%vd_sp sz=1
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VCVT 1111 1110 1.11 11 rm:2 .... 1010 op:1 1.0 .... \
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vm=%vm_sp vd=%vd_sp sz=2
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VCVT 1111 1110 1.11 11 rm:2 .... 1011 op:1 1.0 .... \
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vm=%vm_dp vd=%vd_sp sz=3
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VMOVX 1111 1110 1.11 0000 .... 1010 01 . 0 .... \
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vd=%vd_sp vm=%vm_sp
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VINS 1111 1110 1.11 0000 .... 1010 11 . 0 .... \
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vd=%vd_sp vm=%vm_sp
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