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3b34ee6780
Replace some debug printf() calls by qemu_log_mask(LOG_GUEST_ERROR). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20200524164503.11944-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
119 lines
2.9 KiB
C
119 lines
2.9 KiB
C
/*
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* DMA device simulation in PKUnity SoC
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*
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* Copyright (C) 2010-2012 Guan Xuetao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation, or any later version.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#undef DEBUG_PUV3
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#include "hw/unicore32/puv3.h"
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#include "qemu/module.h"
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#include "qemu/log.h"
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#define PUV3_DMA_CH_NR (6)
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#define PUV3_DMA_CH_MASK (0xff)
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#define PUV3_DMA_CH(offset) ((offset) >> 8)
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#define TYPE_PUV3_DMA "puv3_dma"
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#define PUV3_DMA(obj) OBJECT_CHECK(PUV3DMAState, (obj), TYPE_PUV3_DMA)
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typedef struct PUV3DMAState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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uint32_t reg_CFG[PUV3_DMA_CH_NR];
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} PUV3DMAState;
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static uint64_t puv3_dma_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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PUV3DMAState *s = opaque;
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uint32_t ret = 0;
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assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
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switch (offset & PUV3_DMA_CH_MASK) {
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case 0x10:
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ret = s->reg_CFG[PUV3_DMA_CH(offset)];
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
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__func__, offset);
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}
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DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
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return ret;
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}
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static void puv3_dma_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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PUV3DMAState *s = opaque;
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assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
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switch (offset & PUV3_DMA_CH_MASK) {
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case 0x10:
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s->reg_CFG[PUV3_DMA_CH(offset)] = value;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad write offset 0x%"HWADDR_PRIx"\n",
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__func__, offset);
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}
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DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
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}
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static const MemoryRegionOps puv3_dma_ops = {
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.read = puv3_dma_read,
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.write = puv3_dma_write,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void puv3_dma_realize(DeviceState *dev, Error **errp)
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{
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PUV3DMAState *s = PUV3_DMA(dev);
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int i;
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for (i = 0; i < PUV3_DMA_CH_NR; i++) {
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s->reg_CFG[i] = 0x0;
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}
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memory_region_init_io(&s->iomem, OBJECT(s), &puv3_dma_ops, s, "puv3_dma",
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PUV3_REGS_OFFSET);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
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}
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static void puv3_dma_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = puv3_dma_realize;
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}
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static const TypeInfo puv3_dma_info = {
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.name = TYPE_PUV3_DMA,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PUV3DMAState),
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.class_init = puv3_dma_class_init,
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};
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static void puv3_dma_register_type(void)
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{
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type_register_static(&puv3_dma_info);
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}
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type_init(puv3_dma_register_type)
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