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33595dc9f3
Under some circumstances, we need to direct ISI and DSI interrupts at the hypervisor, turning them into HISI/HDSI, and using different SPRs (HDSISR and HDAR) depending on the combination of MSR_DR and the corresponding VPM bits in LPCR. This moves part of the code into helpers that are fixed to select the right exception type and registers. On pre-P7 processors, LPCR is 0 which provides the old behaviour of directing the interrupts at the supervisor. Thanks to Andrei Warkentin for finding a bug when HV=1 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [clg: Merged a fix on POWERPC_EXCP_HDSI fixing the condition on msr_hv, from Andrei Warkentin <andrey.warkentin@gmail.com> ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> |
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.. | ||
arch_dump.c | ||
cpu-models.c | ||
cpu-models.h | ||
cpu-qom.h | ||
cpu.h | ||
dfp_helper.c | ||
excp_helper.c | ||
fpu_helper.c | ||
gdbstub.c | ||
helper_regs.h | ||
helper.h | ||
int_helper.c | ||
kvm_ppc.h | ||
kvm-stub.c | ||
kvm.c | ||
machine.c | ||
Makefile.objs | ||
mem_helper.c | ||
mfrom_table_gen.c | ||
mfrom_table.c | ||
misc_helper.c | ||
mmu_helper.c | ||
mmu-hash32.c | ||
mmu-hash32.h | ||
mmu-hash64.c | ||
mmu-hash64.h | ||
monitor.c | ||
STATUS | ||
timebase_helper.c | ||
trace-events | ||
translate_init.c | ||
translate.c | ||
user_only_helper.c |