Petar Jovanovic 7f6613cedc target-mips: fix MTHC1 and MFHC1 when FPU in FR=0 mode ...

Previous implementation presumed that FPU registers are 64-bit and are
working in 64-bit mode. This change first checks MIPS_HFLAG_F64 and if not
set, it does load/store from the odd numbered register pair.
Patch by Matthew Fortune.

Signed-off-by: Matthew Fortune <matthew.fortune@imgtec.com>
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

2014-03-25 23:36:35 +01:00

..

cpu-qom.h

cpu: Introduce CPUClass::gdb_{read,write}_register()

2013-07-27 00:04:17 +02:00

cpu.c

cputlb: Change tlb_flush() argument to CPUState

2014-03-13 19:52:47 +01:00

cpu.h

cpu: Move breakpoints field from CPU_COMMON to CPUState

2014-03-13 19:20:47 +01:00

dsp_helper.c

target-mips: Use macro ARRAY_SIZE where possible

2013-12-09 16:44:04 +01:00

gdbstub.c

cpu: Introduce CPUClass::gdb_{read,write}_register()

2013-07-27 00:04:17 +02:00

helper.c

cputlb: Change tlb_set_page() argument to CPUState

2014-03-13 19:52:47 +01:00

helper.h

target-mips: add user-mode FR switch support for MIPS32r5

2014-02-10 16:46:38 +01:00

lmi_helper.c

…

machine.c

cputlb: Change tlb_flush() argument to CPUState

2014-03-13 19:52:47 +01:00

Makefile.objs

cpu: Introduce CPUClass::gdb_{read,write}_register()

2013-07-27 00:04:17 +02:00

mips-defs.h

target-mips: add CPU definition for MIPS32R5

2014-02-10 16:45:53 +01:00

op_helper.c

cputlb: Change tlb_flush() argument to CPUState

2014-03-13 19:52:47 +01:00

TODO

…

translate_init.c

exec: Change cpu_abort() argument to CPUState

2014-03-13 19:52:28 +01:00

translate.c

target-mips: fix MTHC1 and MFHC1 when FPU in FR=0 mode

2014-03-25 23:36:35 +01:00