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Switch the cadence uart to multi-phase reset and add the reference clock input. The input clock frequency is added to the migration structure. The reference clock controls the baudrate generation. If it disabled, any input characters and events are ignored. If this clock remains unconnected, the uart behaves as before (it default to a 50MHz ref clock). Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200406135251.157596-8-damien.hedde@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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| .. | ||
| bcm2835_aux.h | ||
| cadence_uart.h | ||
| cmsdk-apb-uart.h | ||
| digic-uart.h | ||
| escc.h | ||
| imx_serial.h | ||
| lm32_juart.h | ||
| nrf51_uart.h | ||
| parallel.h | ||
| pl011.h | ||
| serial.h | ||
| stm32f2xx_usart.h | ||
| xilinx_uartlite.h | ||