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4246e225c0
Depending on access type raise either InstrPIFDataError or LoadStorePIFDataError exception. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
100 lines
3.6 KiB
C
100 lines
3.6 KiB
C
/*
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* QEMU Xtensa CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef QEMU_XTENSA_CPU_QOM_H
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#define QEMU_XTENSA_CPU_QOM_H
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#include "qom/cpu.h"
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#include "cpu.h"
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#define TYPE_XTENSA_CPU "xtensa-cpu"
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#define XTENSA_CPU_CLASS(class) \
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OBJECT_CLASS_CHECK(XtensaCPUClass, (class), TYPE_XTENSA_CPU)
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#define XTENSA_CPU(obj) \
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OBJECT_CHECK(XtensaCPU, (obj), TYPE_XTENSA_CPU)
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#define XTENSA_CPU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(XtensaCPUClass, (obj), TYPE_XTENSA_CPU)
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/**
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* XtensaCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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* @config: The CPU core configuration.
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*
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* An Xtensa CPU model.
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*/
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typedef struct XtensaCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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void (*parent_reset)(CPUState *cpu);
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const XtensaConfig *config;
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} XtensaCPUClass;
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/**
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* XtensaCPU:
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* @env: #CPUXtensaState
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*
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* An Xtensa CPU.
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*/
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typedef struct XtensaCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUXtensaState env;
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} XtensaCPU;
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static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
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{
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return container_of(env, XtensaCPU, env);
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}
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#define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
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#define ENV_OFFSET offsetof(XtensaCPU, env)
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void xtensa_cpu_do_interrupt(CPUState *cpu);
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bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
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void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr,
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bool is_write, bool is_exec, int opaque,
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unsigned size);
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void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
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fprintf_function cpu_fprintf, int flags);
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hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
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int is_write, int is_user, uintptr_t retaddr);
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#endif
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