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https://github.com/xemu-project/xemu.git
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03dd024ff5
Move the inclusion out of hw/hw.h, most files do not need it. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
461 lines
12 KiB
C
461 lines
12 KiB
C
/*
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* Status and system control registers for Xilinx Zynq Platform
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*
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* Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
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* Copyright (c) 2012 PetaLogix Pty Ltd.
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* Based on hw/arm_sysctl.c, written by Paul Brook
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "qemu/timer.h"
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#include "hw/sysbus.h"
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#include "sysemu/sysemu.h"
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#include "qemu/log.h"
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#ifndef ZYNQ_SLCR_ERR_DEBUG
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#define ZYNQ_SLCR_ERR_DEBUG 0
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#endif
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#define DB_PRINT(...) do { \
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if (ZYNQ_SLCR_ERR_DEBUG) { \
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fprintf(stderr, ": %s: ", __func__); \
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fprintf(stderr, ## __VA_ARGS__); \
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} \
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} while (0);
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#define XILINX_LOCK_KEY 0x767b
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#define XILINX_UNLOCK_KEY 0xdf0d
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#define R_PSS_RST_CTRL_SOFT_RST 0x1
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enum {
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SCL = 0x000 / 4,
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LOCK,
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UNLOCK,
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LOCKSTA,
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ARM_PLL_CTRL = 0x100 / 4,
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DDR_PLL_CTRL,
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IO_PLL_CTRL,
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PLL_STATUS,
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ARM_PLL_CFG,
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DDR_PLL_CFG,
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IO_PLL_CFG,
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ARM_CLK_CTRL = 0x120 / 4,
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DDR_CLK_CTRL,
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DCI_CLK_CTRL,
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APER_CLK_CTRL,
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USB0_CLK_CTRL,
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USB1_CLK_CTRL,
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GEM0_RCLK_CTRL,
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GEM1_RCLK_CTRL,
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GEM0_CLK_CTRL,
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GEM1_CLK_CTRL,
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SMC_CLK_CTRL,
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LQSPI_CLK_CTRL,
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SDIO_CLK_CTRL,
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UART_CLK_CTRL,
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SPI_CLK_CTRL,
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CAN_CLK_CTRL,
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CAN_MIOCLK_CTRL,
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DBG_CLK_CTRL,
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PCAP_CLK_CTRL,
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TOPSW_CLK_CTRL,
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#define FPGA_CTRL_REGS(n, start) \
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FPGA ## n ## _CLK_CTRL = (start) / 4, \
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FPGA ## n ## _THR_CTRL, \
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FPGA ## n ## _THR_CNT, \
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FPGA ## n ## _THR_STA,
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FPGA_CTRL_REGS(0, 0x170)
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FPGA_CTRL_REGS(1, 0x180)
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FPGA_CTRL_REGS(2, 0x190)
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FPGA_CTRL_REGS(3, 0x1a0)
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BANDGAP_TRIP = 0x1b8 / 4,
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PLL_PREDIVISOR = 0x1c0 / 4,
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CLK_621_TRUE,
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PSS_RST_CTRL = 0x200 / 4,
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DDR_RST_CTRL,
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TOPSW_RESET_CTRL,
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DMAC_RST_CTRL,
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USB_RST_CTRL,
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GEM_RST_CTRL,
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SDIO_RST_CTRL,
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SPI_RST_CTRL,
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CAN_RST_CTRL,
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I2C_RST_CTRL,
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UART_RST_CTRL,
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GPIO_RST_CTRL,
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LQSPI_RST_CTRL,
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SMC_RST_CTRL,
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OCM_RST_CTRL,
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FPGA_RST_CTRL = 0x240 / 4,
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A9_CPU_RST_CTRL,
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RS_AWDT_CTRL = 0x24c / 4,
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RST_REASON,
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REBOOT_STATUS = 0x258 / 4,
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BOOT_MODE,
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APU_CTRL = 0x300 / 4,
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WDT_CLK_SEL,
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TZ_DMA_NS = 0x440 / 4,
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TZ_DMA_IRQ_NS,
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TZ_DMA_PERIPH_NS,
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PSS_IDCODE = 0x530 / 4,
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DDR_URGENT = 0x600 / 4,
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DDR_CAL_START = 0x60c / 4,
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DDR_REF_START = 0x614 / 4,
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DDR_CMD_STA,
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DDR_URGENT_SEL,
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DDR_DFI_STATUS,
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MIO = 0x700 / 4,
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#define MIO_LENGTH 54
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MIO_LOOPBACK = 0x804 / 4,
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MIO_MST_TRI0,
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MIO_MST_TRI1,
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SD0_WP_CD_SEL = 0x830 / 4,
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SD1_WP_CD_SEL,
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LVL_SHFTR_EN = 0x900 / 4,
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OCM_CFG = 0x910 / 4,
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CPU_RAM = 0xa00 / 4,
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IOU = 0xa30 / 4,
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DMAC_RAM = 0xa50 / 4,
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AFI0 = 0xa60 / 4,
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AFI1 = AFI0 + 3,
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AFI2 = AFI1 + 3,
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AFI3 = AFI2 + 3,
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#define AFI_LENGTH 3
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OCM = 0xa90 / 4,
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DEVCI_RAM = 0xaa0 / 4,
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CSG_RAM = 0xab0 / 4,
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GPIOB_CTRL = 0xb00 / 4,
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GPIOB_CFG_CMOS18,
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GPIOB_CFG_CMOS25,
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GPIOB_CFG_CMOS33,
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GPIOB_CFG_HSTL = 0xb14 / 4,
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GPIOB_DRVR_BIAS_CTRL,
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DDRIOB = 0xb40 / 4,
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#define DDRIOB_LENGTH 14
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};
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#define ZYNQ_SLCR_MMIO_SIZE 0x1000
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#define ZYNQ_SLCR_NUM_REGS (ZYNQ_SLCR_MMIO_SIZE / 4)
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#define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr"
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#define ZYNQ_SLCR(obj) OBJECT_CHECK(ZynqSLCRState, (obj), TYPE_ZYNQ_SLCR)
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typedef struct ZynqSLCRState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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uint32_t regs[ZYNQ_SLCR_NUM_REGS];
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} ZynqSLCRState;
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static void zynq_slcr_reset(DeviceState *d)
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{
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ZynqSLCRState *s = ZYNQ_SLCR(d);
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int i;
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DB_PRINT("RESET\n");
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s->regs[LOCKSTA] = 1;
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/* 0x100 - 0x11C */
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s->regs[ARM_PLL_CTRL] = 0x0001A008;
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s->regs[DDR_PLL_CTRL] = 0x0001A008;
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s->regs[IO_PLL_CTRL] = 0x0001A008;
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s->regs[PLL_STATUS] = 0x0000003F;
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s->regs[ARM_PLL_CFG] = 0x00014000;
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s->regs[DDR_PLL_CFG] = 0x00014000;
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s->regs[IO_PLL_CFG] = 0x00014000;
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/* 0x120 - 0x16C */
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s->regs[ARM_CLK_CTRL] = 0x1F000400;
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s->regs[DDR_CLK_CTRL] = 0x18400003;
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s->regs[DCI_CLK_CTRL] = 0x01E03201;
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s->regs[APER_CLK_CTRL] = 0x01FFCCCD;
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s->regs[USB0_CLK_CTRL] = s->regs[USB1_CLK_CTRL] = 0x00101941;
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s->regs[GEM0_RCLK_CTRL] = s->regs[GEM1_RCLK_CTRL] = 0x00000001;
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s->regs[GEM0_CLK_CTRL] = s->regs[GEM1_CLK_CTRL] = 0x00003C01;
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s->regs[SMC_CLK_CTRL] = 0x00003C01;
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s->regs[LQSPI_CLK_CTRL] = 0x00002821;
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s->regs[SDIO_CLK_CTRL] = 0x00001E03;
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s->regs[UART_CLK_CTRL] = 0x00003F03;
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s->regs[SPI_CLK_CTRL] = 0x00003F03;
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s->regs[CAN_CLK_CTRL] = 0x00501903;
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s->regs[DBG_CLK_CTRL] = 0x00000F03;
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s->regs[PCAP_CLK_CTRL] = 0x00000F01;
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/* 0x170 - 0x1AC */
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s->regs[FPGA0_CLK_CTRL] = s->regs[FPGA1_CLK_CTRL] = s->regs[FPGA2_CLK_CTRL]
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= s->regs[FPGA3_CLK_CTRL] = 0x00101800;
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s->regs[FPGA0_THR_STA] = s->regs[FPGA1_THR_STA] = s->regs[FPGA2_THR_STA]
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= s->regs[FPGA3_THR_STA] = 0x00010000;
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/* 0x1B0 - 0x1D8 */
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s->regs[BANDGAP_TRIP] = 0x0000001F;
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s->regs[PLL_PREDIVISOR] = 0x00000001;
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s->regs[CLK_621_TRUE] = 0x00000001;
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/* 0x200 - 0x25C */
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s->regs[FPGA_RST_CTRL] = 0x01F33F0F;
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s->regs[RST_REASON] = 0x00000040;
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s->regs[BOOT_MODE] = 0x00000001;
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/* 0x700 - 0x7D4 */
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for (i = 0; i < 54; i++) {
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s->regs[MIO + i] = 0x00001601;
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}
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for (i = 2; i <= 8; i++) {
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s->regs[MIO + i] = 0x00000601;
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}
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s->regs[MIO_MST_TRI0] = s->regs[MIO_MST_TRI1] = 0xFFFFFFFF;
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s->regs[CPU_RAM + 0] = s->regs[CPU_RAM + 1] = s->regs[CPU_RAM + 3]
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= s->regs[CPU_RAM + 4] = s->regs[CPU_RAM + 7]
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= 0x00010101;
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s->regs[CPU_RAM + 2] = s->regs[CPU_RAM + 5] = 0x01010101;
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s->regs[CPU_RAM + 6] = 0x00000001;
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s->regs[IOU + 0] = s->regs[IOU + 1] = s->regs[IOU + 2] = s->regs[IOU + 3]
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= 0x09090909;
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s->regs[IOU + 4] = s->regs[IOU + 5] = 0x00090909;
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s->regs[IOU + 6] = 0x00000909;
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s->regs[DMAC_RAM] = 0x00000009;
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s->regs[AFI0 + 0] = s->regs[AFI0 + 1] = 0x09090909;
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s->regs[AFI1 + 0] = s->regs[AFI1 + 1] = 0x09090909;
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s->regs[AFI2 + 0] = s->regs[AFI2 + 1] = 0x09090909;
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s->regs[AFI3 + 0] = s->regs[AFI3 + 1] = 0x09090909;
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s->regs[AFI0 + 2] = s->regs[AFI1 + 2] = s->regs[AFI2 + 2]
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= s->regs[AFI3 + 2] = 0x00000909;
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s->regs[OCM + 0] = 0x01010101;
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s->regs[OCM + 1] = s->regs[OCM + 2] = 0x09090909;
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s->regs[DEVCI_RAM] = 0x00000909;
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s->regs[CSG_RAM] = 0x00000001;
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s->regs[DDRIOB + 0] = s->regs[DDRIOB + 1] = s->regs[DDRIOB + 2]
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= s->regs[DDRIOB + 3] = 0x00000e00;
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s->regs[DDRIOB + 4] = s->regs[DDRIOB + 5] = s->regs[DDRIOB + 6]
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= 0x00000e00;
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s->regs[DDRIOB + 12] = 0x00000021;
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}
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static bool zynq_slcr_check_offset(hwaddr offset, bool rnw)
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{
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switch (offset) {
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case LOCK:
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case UNLOCK:
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case DDR_CAL_START:
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case DDR_REF_START:
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return !rnw; /* Write only */
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case LOCKSTA:
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case FPGA0_THR_STA:
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case FPGA1_THR_STA:
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case FPGA2_THR_STA:
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case FPGA3_THR_STA:
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case BOOT_MODE:
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case PSS_IDCODE:
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case DDR_CMD_STA:
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case DDR_DFI_STATUS:
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case PLL_STATUS:
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return rnw;/* read only */
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case SCL:
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case ARM_PLL_CTRL ... IO_PLL_CTRL:
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case ARM_PLL_CFG ... IO_PLL_CFG:
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case ARM_CLK_CTRL ... TOPSW_CLK_CTRL:
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case FPGA0_CLK_CTRL ... FPGA0_THR_CNT:
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case FPGA1_CLK_CTRL ... FPGA1_THR_CNT:
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case FPGA2_CLK_CTRL ... FPGA2_THR_CNT:
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case FPGA3_CLK_CTRL ... FPGA3_THR_CNT:
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case BANDGAP_TRIP:
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case PLL_PREDIVISOR:
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case CLK_621_TRUE:
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case PSS_RST_CTRL ... A9_CPU_RST_CTRL:
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case RS_AWDT_CTRL:
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case RST_REASON:
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case REBOOT_STATUS:
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case APU_CTRL:
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case WDT_CLK_SEL:
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case TZ_DMA_NS ... TZ_DMA_PERIPH_NS:
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case DDR_URGENT:
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case DDR_URGENT_SEL:
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case MIO ... MIO + MIO_LENGTH - 1:
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case MIO_LOOPBACK ... MIO_MST_TRI1:
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case SD0_WP_CD_SEL:
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case SD1_WP_CD_SEL:
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case LVL_SHFTR_EN:
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case OCM_CFG:
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case CPU_RAM:
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case IOU:
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case DMAC_RAM:
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case AFI0 ... AFI3 + AFI_LENGTH - 1:
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case OCM:
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case DEVCI_RAM:
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case CSG_RAM:
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case GPIOB_CTRL ... GPIOB_CFG_CMOS33:
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case GPIOB_CFG_HSTL:
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case GPIOB_DRVR_BIAS_CTRL:
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case DDRIOB ... DDRIOB + DDRIOB_LENGTH - 1:
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return true;
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default:
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return false;
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}
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}
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static uint64_t zynq_slcr_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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ZynqSLCRState *s = opaque;
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offset /= 4;
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uint32_t ret = s->regs[offset];
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if (!zynq_slcr_check_offset(offset, true)) {
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qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid read access to "
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" addr %" HWADDR_PRIx "\n", offset * 4);
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}
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DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", offset * 4, ret);
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return ret;
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}
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static void zynq_slcr_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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ZynqSLCRState *s = (ZynqSLCRState *)opaque;
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offset /= 4;
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DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4, val);
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if (!zynq_slcr_check_offset(offset, false)) {
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qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid write access to "
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"addr %" HWADDR_PRIx "\n", offset * 4);
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return;
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}
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switch (offset) {
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case SCL:
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s->regs[SCL] = val & 0x1;
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return;
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case LOCK:
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if ((val & 0xFFFF) == XILINX_LOCK_KEY) {
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DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
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(unsigned)val & 0xFFFF);
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s->regs[LOCKSTA] = 1;
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} else {
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DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
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(int)offset, (unsigned)val & 0xFFFF);
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}
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return;
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case UNLOCK:
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if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) {
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DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
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(unsigned)val & 0xFFFF);
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s->regs[LOCKSTA] = 0;
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} else {
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DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
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(int)offset, (unsigned)val & 0xFFFF);
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}
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return;
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}
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if (s->regs[LOCKSTA]) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"SCLR registers are locked. Unlock them first\n");
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return;
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}
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s->regs[offset] = val;
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switch (offset) {
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case PSS_RST_CTRL:
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if (val & R_PSS_RST_CTRL_SOFT_RST) {
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qemu_system_reset_request();
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}
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break;
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}
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}
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static const MemoryRegionOps slcr_ops = {
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.read = zynq_slcr_read,
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.write = zynq_slcr_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void zynq_slcr_init(Object *obj)
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{
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ZynqSLCRState *s = ZYNQ_SLCR(obj);
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memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr",
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ZYNQ_SLCR_MMIO_SIZE);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
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}
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static const VMStateDescription vmstate_zynq_slcr = {
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.name = "zynq_slcr",
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS),
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VMSTATE_END_OF_LIST()
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}
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};
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static void zynq_slcr_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &vmstate_zynq_slcr;
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dc->reset = zynq_slcr_reset;
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}
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static const TypeInfo zynq_slcr_info = {
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.class_init = zynq_slcr_class_init,
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.name = TYPE_ZYNQ_SLCR,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(ZynqSLCRState),
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.instance_init = zynq_slcr_init,
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};
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static void zynq_slcr_register_types(void)
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{
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type_register_static(&zynq_slcr_info);
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}
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|
|
|
type_init(zynq_slcr_register_types)
|