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25bda50a0c
Such address translation is needed when load address recorded in uImage is a virtual address. When the actual load address is requested, return untranslated address: user that needs the translated address can always apply translation function to it and those that need it untranslated don't need to do the inverse translation. Add translation function pointer and its parameter to uimage_load prototype. Update all existing users. No user-visible functional changes. Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Alexander Graf <agraf@suse.de>
149 lines
4.5 KiB
C
149 lines
4.5 KiB
C
/*
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* OpenRISC simulator for use as an IIS.
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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* Feng Gao <gf91597@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw/hw.h"
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#include "hw/boards.h"
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#include "elf.h"
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#include "hw/char/serial.h"
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#include "net/net.h"
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#include "hw/loader.h"
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#include "exec/address-spaces.h"
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#include "sysemu/sysemu.h"
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#include "hw/sysbus.h"
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#include "sysemu/qtest.h"
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#define KERNEL_LOAD_ADDR 0x100
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static void main_cpu_reset(void *opaque)
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{
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OpenRISCCPU *cpu = opaque;
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cpu_reset(CPU(cpu));
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}
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static void openrisc_sim_net_init(MemoryRegion *address_space,
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hwaddr base,
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hwaddr descriptors,
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qemu_irq irq, NICInfo *nd)
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{
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DeviceState *dev;
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SysBusDevice *s;
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dev = qdev_create(NULL, "open_eth");
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qdev_set_nic_properties(dev, nd);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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sysbus_connect_irq(s, 0, irq);
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memory_region_add_subregion(address_space, base,
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sysbus_mmio_get_region(s, 0));
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memory_region_add_subregion(address_space, descriptors,
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sysbus_mmio_get_region(s, 1));
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}
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static void cpu_openrisc_load_kernel(ram_addr_t ram_size,
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const char *kernel_filename,
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OpenRISCCPU *cpu)
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{
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long kernel_size;
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uint64_t elf_entry;
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hwaddr entry;
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if (kernel_filename && !qtest_enabled()) {
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kernel_size = load_elf(kernel_filename, NULL, NULL,
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&elf_entry, NULL, NULL, 1, ELF_MACHINE, 1);
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entry = elf_entry;
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if (kernel_size < 0) {
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kernel_size = load_uimage(kernel_filename,
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&entry, NULL, NULL, NULL, NULL);
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}
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if (kernel_size < 0) {
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kernel_size = load_image_targphys(kernel_filename,
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KERNEL_LOAD_ADDR,
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ram_size - KERNEL_LOAD_ADDR);
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entry = KERNEL_LOAD_ADDR;
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}
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if (kernel_size < 0) {
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fprintf(stderr, "QEMU: couldn't load the kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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cpu->env.pc = entry;
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}
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}
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static void openrisc_sim_init(MachineState *machine)
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{
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ram_addr_t ram_size = machine->ram_size;
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const char *cpu_model = machine->cpu_model;
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const char *kernel_filename = machine->kernel_filename;
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OpenRISCCPU *cpu = NULL;
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MemoryRegion *ram;
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int n;
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if (!cpu_model) {
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cpu_model = "or1200";
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}
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for (n = 0; n < smp_cpus; n++) {
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cpu = cpu_openrisc_init(cpu_model);
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if (cpu == NULL) {
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fprintf(stderr, "Unable to find CPU definition!\n");
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exit(1);
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}
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qemu_register_reset(main_cpu_reset, cpu);
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main_cpu_reset(cpu);
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}
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ram = g_malloc(sizeof(*ram));
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memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_abort);
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vmstate_register_ram_global(ram);
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memory_region_add_subregion(get_system_memory(), 0, ram);
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cpu_openrisc_pic_init(cpu);
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cpu_openrisc_clock_init(cpu);
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serial_mm_init(get_system_memory(), 0x90000000, 0, cpu->env.irq[2],
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115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
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if (nd_table[0].used) {
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openrisc_sim_net_init(get_system_memory(), 0x92000000,
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0x92000400, cpu->env.irq[4], nd_table);
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}
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cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
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}
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static QEMUMachine openrisc_sim_machine = {
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.name = "or32-sim",
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.desc = "or32 simulation",
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.init = openrisc_sim_init,
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.max_cpus = 1,
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.is_default = 1,
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};
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static void openrisc_sim_machine_init(void)
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{
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qemu_register_machine(&openrisc_sim_machine);
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}
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machine_init(openrisc_sim_machine_init);
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