xemu/target-arm
Peter Maydell 3b77157964 target-arm: Implement XScale cache lockdown operations as NOPs
XScale defines some implementation-specific coprocessor registers
for doing cache lockdown operations. Since QEMU doesn't model a
cache no proper implementation is possible, but NOP out the
registers so that guest code like u-boot that tries to use them
doesn't crash.

Reported-by: <prqek@centrum.cz>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-05-01 15:24:44 +01:00
..
2014-03-17 16:31:53 +00:00
2013-09-25 21:23:05 +02:00
2014-04-17 21:34:04 +01:00
2014-04-17 21:34:04 +01:00
2014-02-26 17:20:00 +00:00
2014-02-26 17:20:00 +00:00
2011-07-23 11:26:12 -05:00