Max Filippov 4be4c5b826 tests/tcg/xtensa: fix vectors and checks in timer test ... Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>		2022-05-06 15:27:40 -07:00
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crt.S
fpu.h
linker.ld.S
macros.inc
Makefile.softmmu-target
test_b.S
test_bi.S
test_boolean.S
test_break.S	tests/tcg/xtensa: fix watchpoint test	2022-05-06 15:27:40 -07:00
test_bz.S
test_cache.S
test_clamps.S
test_dfp0_arith.S
test_exclusive.S
test_extui.S
test_flix.S
test_fp0_arith.S
test_fp0_conv.S
test_fp0_div.S
test_fp0_sqrt.S
test_fp1.S
test_fp_cpenable.S
test_interrupt.S
test_load_store.S
test_loop.S
test_lsc.S
test_mac16.S
test_max.S
test_min.S
test_mmu.S	tests/tcg/xtensa: enable mmu tests for MMUv3	2022-05-06 15:27:40 -07:00
test_mul16.S
test_mul32.S
test_nsa.S
test_phys_mem.S	tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3	2022-05-06 15:27:40 -07:00
test_quo.S
test_rem.S
test_rst0.S
test_s32c1i.S
test_sar.S
test_sext.S
test_shift.S
test_sr.S	tests/tcg/xtensa: restore vecbase SR after test	2022-05-06 15:27:40 -07:00
test_timer.S	tests/tcg/xtensa: fix vectors and checks in timer test	2022-05-06 15:27:40 -07:00
test_windowed.S
vectors.S