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47c66009ab
Unify half a dozen copies of very similar code (the only difference being whether comparisons were case-sensitive) and use it also in Tricore, which did not do any sorting of CPU model names. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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| .. | ||
| cpu-qom.h | ||
| cpu.c | ||
| cpu.h | ||
| gdbstub.c | ||
| helper.c | ||
| helper.h | ||
| lm32-semi.c | ||
| machine.c | ||
| Makefile.objs | ||
| op_helper.c | ||
| README | ||
| TODO | ||
| translate.c | ||
LatticeMico32 target -------------------- General ------- All opcodes including the JUART CSRs are supported. JTAG UART --------- JTAG UART is routed to a serial console device. For the current boards it is the second one. Ie to enable it in the qemu virtual console window use the following command line parameters: -serial vc -serial vc This will make serial0 (the lm32_uart) and serial1 (the JTAG UART) available as virtual consoles. Semihosting ----------- Semihosting on this target is supported. Some system calls like read, write and exit are executed on the host if semihosting is enabled. See target/lm32-semi.c for all supported system calls. Emulation aware programs can use this mechanism to shut down the virtual machine and print to the host console. See the tcg tests for an example. Special instructions -------------------- The translation recognizes one special instruction to halt the cpu: and r0, r0, r0 On real hardware this instruction is a nop. It is not used by GCC and should (hopefully) not be used within hand-crafted assembly. Insert this instruction in your idle loop to reduce the cpu load on the host. Ignoring the MSB of the address bus ----------------------------------- Some SoC ignores the MSB on the address bus. Thus creating a shadow memory area. As a general rule, 0x00000000-0x7fffffff is cached, whereas 0x80000000-0xffffffff is not cached and used to access IO devices. This behaviour can be enabled with: cpu_lm32_set_phys_msb_ignore(env, 1);