Lara Lazier 498df2a747 target/i386: Added consistency checks for CR0 ...

The combination of unset CD and set NW bit in CR0 is illegal.
CR0[63:32] are also reserved and need to be zero.
(AMD64 Architecture Programmer's Manual, V2, 15.5)

Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Message-Id: <20210616123907.17765-4-laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

2021-06-16 15:02:40 +02:00

..

alpha

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

arm

target/arm: Enable BFloat16 extensions

2021-06-03 16:43:26 +01:00

avr

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

cris

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

hexagon

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

hppa

target/hppa: Remove unused 'memory.h' header

2021-06-05 21:23:14 +02:00

i386

target/i386: Added consistency checks for CR0

2021-06-16 15:02:40 +02:00

m68k

softfloat: Introduce Floatx80RoundPrec

2021-06-03 14:04:02 -07:00

microblaze

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

mips

target/mips: Fix 'Uncoditional' typo

2021-06-05 21:28:54 +02:00

nios2

target/nios2: fix page-fit instruction count

2021-06-05 21:17:10 +02:00

openrisc

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

ppc

target/ppc: fix single-step exception regression

2021-06-03 18:10:31 +10:00

riscv

target/riscv: rvb: add b-ext version cpu option

2021-06-08 09:59:46 +10:00

rx

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

s390x

docs: fix references to docs/devel/tracing.rst

2021-06-02 06:51:09 +02:00

sh4

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

sparc

docs: fix references to docs/devel/tracing.rst

2021-06-02 06:51:09 +02:00

tricore

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

xtensa

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

meson.build

…