Stefan Hajnoczi 4a9c04672a Cache CPUClass for use in hot code paths. ... Add CPUTLBEntryFull, probe_access_full, tlb_set_page_full. Add generic support for TARGET_TB_PCREL. tcg/ppc: Optimize 26-bit jumps using STQ for POWER 2.07 target/sh4: Fix TB_FLAG_UNALIGN -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmM8jXEdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/oEggArAHK8FtydfQ4ZwnF SjXfpdP50OC0SZn3uBN93FZOrxz9UYG9t1oDHs39J/+b/u2nwJYch//EH2k+NtOW hc3iIgS9bWgs/UWZESkViKQccw7gpYlc21Br38WWwFNEFyecX0p+e9pJgld5rSv1 mRGvCs5J2svH2tcXl/Sb/JWgcumOJoG7qy2aLyJGolR6UOfwcfFMzQXzq8qjpRKH Jh84qusE/rLbzBsdN6snJY4+dyvUo03lT5IJ4d+FQg2tUip+Qqt7pnMbsqq6qF6H R6fWU1JTbsh7GxXJwQJ83jLBnUsi8cy6FKrZ3jyiBq76+DIpR0PqoEe+PN/weInU TN0z4g== =RfXJ -----END PGP SIGNATURE----- Merge tag 'pull-tcg-20221004' of https://gitlab.com/rth7680/qemu into staging Cache CPUClass for use in hot code paths. Add CPUTLBEntryFull, probe_access_full, tlb_set_page_full. Add generic support for TARGET_TB_PCREL. tcg/ppc: Optimize 26-bit jumps using STQ for POWER 2.07 target/sh4: Fix TB_FLAG_UNALIGN # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmM8jXEdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/oEggArAHK8FtydfQ4ZwnF # SjXfpdP50OC0SZn3uBN93FZOrxz9UYG9t1oDHs39J/+b/u2nwJYch//EH2k+NtOW # hc3iIgS9bWgs/UWZESkViKQccw7gpYlc21Br38WWwFNEFyecX0p+e9pJgld5rSv1 # mRGvCs5J2svH2tcXl/Sb/JWgcumOJoG7qy2aLyJGolR6UOfwcfFMzQXzq8qjpRKH # Jh84qusE/rLbzBsdN6snJY4+dyvUo03lT5IJ4d+FQg2tUip+Qqt7pnMbsqq6qF6H # R6fWU1JTbsh7GxXJwQJ83jLBnUsi8cy6FKrZ3jyiBq76+DIpR0PqoEe+PN/weInU # TN0z4g== # =RfXJ # -----END PGP SIGNATURE----- # gpg: Signature made Tue 04 Oct 2022 15:45:53 EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20221004' of https://gitlab.com/rth7680/qemu: target/sh4: Fix TB_FLAG_UNALIGN tcg/ppc: Optimize 26-bit jumps accel/tcg: Introduce TARGET_TB_PCREL accel/tcg: Introduce tb_pc and log_pc hw/core: Add CPUClass.get_pc include/hw/core: Create struct CPUJumpCache accel/tcg: Inline tb_flush_jmp_cache accel/tcg: Do not align tb->page_addr[0] accel/tcg: Use DisasContextBase in plugin_gen_tb_start accel/tcg: Use bool for page_find_alloc accel/tcg: Remove PageDesc code_bitmap include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA accel/tcg: Introduce tlb_set_page_full accel/tcg: Introduce probe_access_full accel/tcg: Suppress auto-invalidate in probe_access_internal accel/tcg: Drop addr member from SavedIOTLB accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull cputlb: used cached CPUClass in our hot-paths hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs cpu: cache CPUClass in CPUState for hot code paths Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>		2022-10-05 10:17:02 -04:00
..
hax	Clean up header guards that don't match their file name	2022-05-11 16:49:06 +02:00
hvf	hvf: Enable RDTSCP support	2022-07-13 00:05:39 +02:00
kvm	Pull request trivial patches branch 20220930-v2	2022-10-04 14:04:18 -04:00
nvmm	Clean up header guards that don't match their file name	2022-05-11 16:49:06 +02:00
tcg	accel/tcg: Introduce tb_pc and log_pc	2022-10-04 12:13:12 -07:00
whpx	Drop superfluous conditionals around g_free()	2022-10-04 00:10:11 +02:00
arch_dump.c	dump: add kernel_gs_base to QEMU CPU state	2018-07-16 16:13:34 +02:00
arch_memory_mapping.c	exec,dump,i386,ppc,s390x: don't include exec/cpu-all.h explicitly	2017-09-19 18:21:33 +02:00
cpu-dump.c	monitor: Trim some trailing space from human-readable output	2021-10-31 21:05:40 +01:00
cpu-internal.h	i386: split off sysemu part of cpu.c	2021-05-10 15:41:52 -04:00
cpu-param.h	Normalize header guard symbol definition	2022-05-11 16:50:26 +02:00
cpu-qom.h	target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro	2022-03-06 22:23:09 +01:00
cpu-sysemu.c	Fix 'writeable' typos	2022-06-08 19:38:47 +01:00
cpu.c	hw/core: Add CPUClass.get_pc	2022-10-04 12:13:12 -07:00
cpu.h	i386: Hyper-V Direct TLB flush hypercall	2022-05-25 21:26:35 +02:00
gdbstub.c	target/i386: fix byte swap issue with XMM register access	2022-04-20 16:04:20 +01:00
helper.c	* Improve virtio-net failover test	2022-02-22 13:07:32 +00:00
helper.h	target/i386: Drop check for singlestep_enabled	2021-10-15 16:39:14 -07:00
host-cpu.c	i386: do not call cpudef-only models functions for max, host, base	2021-07-23 15:47:13 +02:00
host-cpu.h	accel-cpu: make cpu_realizefn return a bool	2021-05-10 15:41:50 -04:00
Kconfig	meson: Introduce target-specific Kconfig	2021-07-09 18:21:34 +02:00
machine.c	target/i386: Enable Arch LBR migration states in vmstate	2022-05-14 12:32:41 +02:00
meson.build	target/i386/sev: Remove stubs by using code elision	2021-10-13 10:47:49 +02:00
monitor.c	monitor: remove 'info ioapic' HMP command	2021-11-02 15:55:13 +00:00
ops_sse_header.h	target/i386: fix INSERTQ implementation	2022-09-19 15:16:00 +02:00
ops_sse.h	target/i386: fix INSERTQ implementation	2022-09-19 15:16:00 +02:00
sev-sysemu-stub.c	monitor: Reduce hmp_info_sev() declaration	2021-10-13 10:47:49 +02:00
sev.c	qapi, target/i386/sev: Add cpu0-id to query-sev-capabilities	2022-04-06 10:50:37 +02:00
sev.h	Clean up header guards that don't match their file name	2022-05-11 16:49:06 +02:00
shift_helper_template.h	x86 tcg cpus: Fix Lesser GPL version number	2020-11-15 16:41:42 +01:00
svm.h	target/i386: Added vVMLOAD and vVMSAVE feature	2021-09-13 13:56:26 +02:00
trace-events	* Update the references to some doc files (use *.rst instead of *.txt)	2021-06-02 17:08:11 +01:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
xsave_helper.c	x86: add support for KVM_CAP_XSAVE2 and AMX state migration	2022-03-15 11:50:50 +01:00