Michael Clark a88365c199 RISC-V: Implement existential predicates for CSRs ... CSR predicate functions are added to the CSR table. mstatus.FS and counter enable checks are moved to predicate functions and two new predicates are added to check misa.S for s* CSRs and a new PMP CPU feature for pmp* CSRs. Processors that don't implement S-mode will trap on access to s* CSRs and processors that don't implement PMP will trap on accesses to pmp* CSRs. PMP checks are disabled in riscv_cpu_handle_mmu_fault when the PMP CPU feature is not present. Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-01-09 10:00:56 -08:00
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cpu_bits.h	RISC-V: Update CSR and interrupt definitions	2018-10-17 13:02:19 -07:00
cpu_helper.c	RISC-V: Implement existential predicates for CSRs	2019-01-09 10:00:56 -08:00
cpu_user.h	RISC-V Linux User Emulation	2018-03-07 08:30:28 +13:00
cpu.c	RISC-V: Implement existential predicates for CSRs	2019-01-09 10:00:56 -08:00
cpu.h	RISC-V: Implement existential predicates for CSRs	2019-01-09 10:00:56 -08:00
csr.c	RISC-V: Implement existential predicates for CSRs	2019-01-09 10:00:56 -08:00
fpu_helper.c	Clean up includes	2018-12-20 10:29:08 +01:00
gdbstub.c	RISC-V: Implement modular CSR helper interface	2019-01-08 13:59:09 -08:00
helper.h	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
instmap.h	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00
Makefile.objs	RISC-V: Implement modular CSR helper interface	2019-01-08 13:59:09 -08:00
op_helper.c	RISC-V: Implement modular CSR helper interface	2019-01-08 13:59:09 -08:00
pmp.c	target/riscv/pmp.c: Fix pmp_decode_napot()	2018-12-20 12:26:39 -08:00
pmp.h	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
translate.c	RISC-V: Respect fences for user-only emulators	2018-11-13 15:12:15 -08:00