Bastian Koppelmann 4d108fe33a target-tricore: Add instructions of RRRR opcode format ... Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>		2015-03-16 15:44:48 +00:00
..
cpu-qom.h	target-tricore: Remove the dummy interrupt boilerplate	2014-09-25 18:54:22 +01:00
cpu.c	target-tricore: Several translator and cpu model fixes	2015-01-26 19:56:45 +00:00
cpu.h	cpu: Make cpu_init() return QOM CPUState object	2015-03-10 17:33:51 +01:00
csfr.def	target-tricore: Fix new typos	2015-01-15 10:44:13 +03:00
helper.c	target-tricore: Remove the dummy interrupt boilerplate	2014-09-25 18:54:22 +01:00
helper.h	target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as first opcode	2015-03-16 15:44:48 +00:00
Makefile.objs	target-tricore: Add target stubs and qom-cpu	2014-09-01 14:49:20 +01:00
op_helper.c	target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as first opcode	2015-03-16 15:44:48 +00:00
translate.c	target-tricore: Add instructions of RRRR opcode format	2015-03-16 15:44:48 +00:00
tricore-defs.h	target-tricore: Add target stubs and qom-cpu	2014-09-01 14:49:20 +01:00
tricore-opcodes.h	target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as first opcode	2015-03-16 15:44:48 +00:00