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4d1df88b63
It adds the Naples chip which supports proper LPC interrupts via the LPC controller rather than via an external CPLD. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: - updated for qemu-2.9 - ported on latest PowerNV patchset - moved the IRQ handler in pnv_lpc.c - introduced pnv_lpc_isa_irq_create() to create the ISA IRQs ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> |
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fdt.h | ||
mac_dbdma.h | ||
openpic.h | ||
pnv_core.h | ||
pnv_lpc.h | ||
pnv_occ.h | ||
pnv_psi.h | ||
pnv_xscom.h | ||
pnv.h | ||
ppc4xx.h | ||
ppc_e500.h | ||
ppc.h | ||
spapr_cpu_core.h | ||
spapr_drc.h | ||
spapr_ovec.h | ||
spapr_rtas.h | ||
spapr_vio.h | ||
spapr.h | ||
xics.h |