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xemu/hw/cpu
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Peter Maydell a55c910e0b hw/intc/arm_gic.c: Implement GICv2 GICC_DIR 
The GICv2 introduces a new CPU interface register GICC_DIR, which
allows an OS to split the "priority drop" and "deactivate interrupt"
parts of interrupt completion. Implement this register.
(Note that the register is at offset 0x1000 in the CPU interface,
which means it is on a different 4K page from all the other registers.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1456854176-7813-1-git-send-email-peter.maydell@linaro.org
2016-03-04 11:30:22 +00:00
..
a9mpcore.c arm devices: Clean up includes 2016-01-29 15:07:25 +00:00
a15mpcore.c hw/intc/arm_gic.c: Implement GICv2 GICC_DIR 2016-03-04 11:30:22 +00:00
arm11mpcore.c arm devices: Clean up includes 2016-01-29 15:07:25 +00:00
Makefile.objs icc_bus: drop the unused files 2015-10-02 16:22:02 -03:00
realview_mpcore.c arm devices: Clean up includes 2016-01-29 15:07:25 +00:00