Ben Widawsky 6a5b19ca63 pci: Disallow improper BAR registration for type 1 ... Prevent future developers working on root complexes, root ports, or bridges that also wish to implement a BAR for those, from shooting themselves in the foot. PCI type 1 headers only support 2 base address registers. It is incorrect and difficult to figure out what is wrong with the device when this mistake is made. With this, it is immediate and obvious what has gone wrong. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Message-Id: <20201015181411.89104-2-ben.widawsky@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2020-10-30 06:48:53 -04:00
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Kconfig	kconfig: add CONFIG_MSI_NONBROKEN	2019-03-18 09:39:57 +01:00
meson.build	meson: convert hw/pci	2020-08-21 06:30:28 -04:00
msi.c	pci/msi: export msi_is_masked()	2019-02-05 10:58:33 -05:00
msix.c	* Miscellaneous fixes and feature enablement (many)	2020-06-12 23:06:22 +01:00
pci_bridge.c	hw/pci/pci_bridge: Use the IEC binary prefix definitions	2020-06-09 14:18:04 -04:00
pci_host.c	hw/pci-host: save/restore pci host config register	2020-07-27 10:24:39 -04:00
pci-stub.c	qapi: Extract PCI commands to 'pci.json'	2020-09-29 15:41:36 +02:00
pci.c	pci: Disallow improper BAR registration for type 1	2020-10-30 06:48:53 -04:00
pcie_aer.c	Include migration/vmstate.h less	2019-08-16 13:31:52 +02:00
pcie_host.c	Include hw/hw.h exactly where needed	2019-08-16 13:31:52 +02:00
pcie_port.c	pcie_root_port: Add hotplug disabling option	2020-03-08 09:18:29 -04:00
pcie.c	pci: advertise a page aligned ATS	2020-10-30 06:48:53 -04:00
shpc.c	qdev: Drop qbus_set_hotplug_handler() parameter @errp	2020-07-02 06:25:29 +02:00
slotid_cap.c	pci: Convert shpc_init() to Error	2017-07-03 22:29:49 +03:00
trace-events	trace-events: Shorten file names in comments	2019-03-22 16:18:07 +00:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00