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xemu/target
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Stephen Long 50d102bd42 target/arm: Implement SVE2 fp multiply-add long 
Implements both vectored and indexed FMLALB, FMLALT, FMLSLB, FMLSLT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-83-richard.henderson@linaro.org
Message-Id: <20200504171240.11220-1-steplong@quicinc.com>
[rth: Rearrange to use float16_to_float32_by_bits.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25 16:01:44 +01:00
..
alpha
target/alpha: fix icount handling for timer instructions
2021-04-05 07:32:56 -07:00
arm
target/arm: Implement SVE2 fp multiply-add long
2021-05-25 16:01:44 +01:00
avr
target/avr: Ignore unimplemented WDR opcode
2021-05-13 19:18:42 +02:00
cris
target/cris: Plug leakage of TCG temporaries
2021-02-22 09:04:58 +01:00
hexagon
Trivial patches pull request 20210503
2021-05-05 13:52:00 +01:00
hppa
…
i386
s390x fixes and cleanups; also related fixes in xtensa,
2021-05-20 18:42:00 +01:00
m68k
Prepare MacOS ROM support:
2021-03-12 18:56:56 +00:00
microblaze
…
mips
target/mips: Set set_default_nan_mode with set_snan_bit_is_one
2021-05-16 07:13:51 -05:00
nios2
semihosting: Move include/hw/semihosting/ -> include/semihosting/
2021-03-10 15:34:12 +00:00
openrisc
Do not include sysemu/sysemu.h if it's not really necessary
2021-05-02 17:24:50 +02:00
ppc
target/ppc: Remove type argument for mmubooke206_get_physical_address
2021-05-19 12:52:07 +10:00
riscv
target/riscv: Fix the RV64H decode comment
2021-05-11 20:02:07 +10:00
rx
Do not include sysemu/sysemu.h if it's not really necessary
2021-05-02 17:24:50 +02:00
s390x
target/s390x: Fix translation exception on illegal instruction
2021-05-20 14:19:30 +02:00
sh4
target/sh4: Return error if CPUClass::get_phys_page_debug() fails
2021-05-13 19:00:50 +02:00
sparc
hw/sparc*: Move cpu_check_irqs() to target/sparc/
2021-05-04 22:45:53 +01:00
tricore
target/tricore: Fix OPC2_32_RRPW_EXTR for width=0
2021-03-14 14:49:01 +01:00
xtensa
target/xtensa: clean up unaligned access
2021-05-20 13:02:58 -07:00
meson.build
Drop the deprecated unicore32 target
2021-05-12 18:20:52 +02:00