mirror of
https://github.com/xemu-project/xemu.git
synced 2024-11-24 03:59:52 +00:00
fcf5ef2ab5
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [crisµblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
217 lines
7.8 KiB
C
217 lines
7.8 KiB
C
/*
|
|
* Copyright 2011 Tilera Corporation. All Rights Reserved.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License
|
|
* as published by the Free Software Foundation, version 2.
|
|
*
|
|
* This program is distributed in the hope that it will be useful, but
|
|
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
|
|
* NON INFRINGEMENT. See the GNU General Public License for
|
|
* more details.
|
|
*/
|
|
|
|
#ifndef __DOXYGEN__
|
|
|
|
#ifndef __ARCH_SPR_DEF_64_H__
|
|
#define __ARCH_SPR_DEF_64_H__
|
|
|
|
#define SPR_AUX_PERF_COUNT_0 0x2105
|
|
#define SPR_AUX_PERF_COUNT_1 0x2106
|
|
#define SPR_AUX_PERF_COUNT_CTL 0x2107
|
|
#define SPR_AUX_PERF_COUNT_STS 0x2108
|
|
#define SPR_CMPEXCH_VALUE 0x2780
|
|
#define SPR_CYCLE 0x2781
|
|
#define SPR_DONE 0x2705
|
|
#define SPR_DSTREAM_PF 0x2706
|
|
#define SPR_EVENT_BEGIN 0x2782
|
|
#define SPR_EVENT_END 0x2783
|
|
#define SPR_EX_CONTEXT_0_0 0x2580
|
|
#define SPR_EX_CONTEXT_0_1 0x2581
|
|
#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0
|
|
#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3
|
|
#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3
|
|
#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2
|
|
#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1
|
|
#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4
|
|
#define SPR_EX_CONTEXT_1_0 0x2480
|
|
#define SPR_EX_CONTEXT_1_1 0x2481
|
|
#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0
|
|
#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3
|
|
#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3
|
|
#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2
|
|
#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1
|
|
#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4
|
|
#define SPR_EX_CONTEXT_2_0 0x2380
|
|
#define SPR_EX_CONTEXT_2_1 0x2381
|
|
#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0
|
|
#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3
|
|
#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3
|
|
#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2
|
|
#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1
|
|
#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4
|
|
#define SPR_FAIL 0x2707
|
|
#define SPR_IDN_AVAIL_EN 0x1a05
|
|
#define SPR_IDN_DATA_AVAIL 0x0a80
|
|
#define SPR_IDN_DEADLOCK_TIMEOUT 0x1806
|
|
#define SPR_IDN_DEMUX_COUNT_0 0x0a05
|
|
#define SPR_IDN_DEMUX_COUNT_1 0x0a06
|
|
#define SPR_IDN_DIRECTION_PROTECT 0x1405
|
|
#define SPR_IDN_PENDING 0x0a08
|
|
#define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1
|
|
#define SPR_INTCTRL_0_STATUS 0x2505
|
|
#define SPR_INTCTRL_1_STATUS 0x2405
|
|
#define SPR_INTCTRL_2_STATUS 0x2305
|
|
#define SPR_INTERRUPT_CRITICAL_SECTION 0x2708
|
|
#define SPR_INTERRUPT_MASK_0 0x2506
|
|
#define SPR_INTERRUPT_MASK_1 0x2406
|
|
#define SPR_INTERRUPT_MASK_2 0x2306
|
|
#define SPR_INTERRUPT_MASK_RESET_0 0x2507
|
|
#define SPR_INTERRUPT_MASK_RESET_1 0x2407
|
|
#define SPR_INTERRUPT_MASK_RESET_2 0x2307
|
|
#define SPR_INTERRUPT_MASK_SET_0 0x2508
|
|
#define SPR_INTERRUPT_MASK_SET_1 0x2408
|
|
#define SPR_INTERRUPT_MASK_SET_2 0x2308
|
|
#define SPR_INTERRUPT_VECTOR_BASE_0 0x2509
|
|
#define SPR_INTERRUPT_VECTOR_BASE_1 0x2409
|
|
#define SPR_INTERRUPT_VECTOR_BASE_2 0x2309
|
|
#define SPR_INTERRUPT_VECTOR_BASE_3 0x2209
|
|
#define SPR_IPI_EVENT_0 0x1f05
|
|
#define SPR_IPI_EVENT_1 0x1e05
|
|
#define SPR_IPI_EVENT_2 0x1d05
|
|
#define SPR_IPI_EVENT_RESET_0 0x1f06
|
|
#define SPR_IPI_EVENT_RESET_1 0x1e06
|
|
#define SPR_IPI_EVENT_RESET_2 0x1d06
|
|
#define SPR_IPI_EVENT_SET_0 0x1f07
|
|
#define SPR_IPI_EVENT_SET_1 0x1e07
|
|
#define SPR_IPI_EVENT_SET_2 0x1d07
|
|
#define SPR_IPI_MASK_0 0x1f08
|
|
#define SPR_IPI_MASK_1 0x1e08
|
|
#define SPR_IPI_MASK_2 0x1d08
|
|
#define SPR_IPI_MASK_RESET_0 0x1f09
|
|
#define SPR_IPI_MASK_RESET_1 0x1e09
|
|
#define SPR_IPI_MASK_RESET_2 0x1d09
|
|
#define SPR_IPI_MASK_SET_0 0x1f0a
|
|
#define SPR_IPI_MASK_SET_1 0x1e0a
|
|
#define SPR_IPI_MASK_SET_2 0x1d0a
|
|
#define SPR_MPL_AUX_PERF_COUNT_SET_0 0x2100
|
|
#define SPR_MPL_AUX_PERF_COUNT_SET_1 0x2101
|
|
#define SPR_MPL_AUX_PERF_COUNT_SET_2 0x2102
|
|
#define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700
|
|
#define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701
|
|
#define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702
|
|
#define SPR_MPL_IDN_ACCESS_SET_0 0x0a00
|
|
#define SPR_MPL_IDN_ACCESS_SET_1 0x0a01
|
|
#define SPR_MPL_IDN_ACCESS_SET_2 0x0a02
|
|
#define SPR_MPL_IDN_AVAIL_SET_0 0x1a00
|
|
#define SPR_MPL_IDN_AVAIL_SET_1 0x1a01
|
|
#define SPR_MPL_IDN_AVAIL_SET_2 0x1a02
|
|
#define SPR_MPL_IDN_COMPLETE_SET_0 0x0500
|
|
#define SPR_MPL_IDN_COMPLETE_SET_1 0x0501
|
|
#define SPR_MPL_IDN_COMPLETE_SET_2 0x0502
|
|
#define SPR_MPL_IDN_FIREWALL_SET_0 0x1400
|
|
#define SPR_MPL_IDN_FIREWALL_SET_1 0x1401
|
|
#define SPR_MPL_IDN_FIREWALL_SET_2 0x1402
|
|
#define SPR_MPL_IDN_TIMER_SET_0 0x1800
|
|
#define SPR_MPL_IDN_TIMER_SET_1 0x1801
|
|
#define SPR_MPL_IDN_TIMER_SET_2 0x1802
|
|
#define SPR_MPL_INTCTRL_0_SET_0 0x2500
|
|
#define SPR_MPL_INTCTRL_0_SET_1 0x2501
|
|
#define SPR_MPL_INTCTRL_0_SET_2 0x2502
|
|
#define SPR_MPL_INTCTRL_1_SET_0 0x2400
|
|
#define SPR_MPL_INTCTRL_1_SET_1 0x2401
|
|
#define SPR_MPL_INTCTRL_1_SET_2 0x2402
|
|
#define SPR_MPL_INTCTRL_2_SET_0 0x2300
|
|
#define SPR_MPL_INTCTRL_2_SET_1 0x2301
|
|
#define SPR_MPL_INTCTRL_2_SET_2 0x2302
|
|
#define SPR_MPL_IPI_0 0x1f04
|
|
#define SPR_MPL_IPI_0_SET_0 0x1f00
|
|
#define SPR_MPL_IPI_0_SET_1 0x1f01
|
|
#define SPR_MPL_IPI_0_SET_2 0x1f02
|
|
#define SPR_MPL_IPI_1 0x1e04
|
|
#define SPR_MPL_IPI_1_SET_0 0x1e00
|
|
#define SPR_MPL_IPI_1_SET_1 0x1e01
|
|
#define SPR_MPL_IPI_1_SET_2 0x1e02
|
|
#define SPR_MPL_IPI_2 0x1d04
|
|
#define SPR_MPL_IPI_2_SET_0 0x1d00
|
|
#define SPR_MPL_IPI_2_SET_1 0x1d01
|
|
#define SPR_MPL_IPI_2_SET_2 0x1d02
|
|
#define SPR_MPL_PERF_COUNT_SET_0 0x2000
|
|
#define SPR_MPL_PERF_COUNT_SET_1 0x2001
|
|
#define SPR_MPL_PERF_COUNT_SET_2 0x2002
|
|
#define SPR_MPL_UDN_ACCESS_SET_0 0x0b00
|
|
#define SPR_MPL_UDN_ACCESS_SET_1 0x0b01
|
|
#define SPR_MPL_UDN_ACCESS_SET_2 0x0b02
|
|
#define SPR_MPL_UDN_AVAIL_SET_0 0x1b00
|
|
#define SPR_MPL_UDN_AVAIL_SET_1 0x1b01
|
|
#define SPR_MPL_UDN_AVAIL_SET_2 0x1b02
|
|
#define SPR_MPL_UDN_COMPLETE_SET_0 0x0600
|
|
#define SPR_MPL_UDN_COMPLETE_SET_1 0x0601
|
|
#define SPR_MPL_UDN_COMPLETE_SET_2 0x0602
|
|
#define SPR_MPL_UDN_FIREWALL_SET_0 0x1500
|
|
#define SPR_MPL_UDN_FIREWALL_SET_1 0x1501
|
|
#define SPR_MPL_UDN_FIREWALL_SET_2 0x1502
|
|
#define SPR_MPL_UDN_TIMER_SET_0 0x1900
|
|
#define SPR_MPL_UDN_TIMER_SET_1 0x1901
|
|
#define SPR_MPL_UDN_TIMER_SET_2 0x1902
|
|
#define SPR_MPL_WORLD_ACCESS_SET_0 0x2700
|
|
#define SPR_MPL_WORLD_ACCESS_SET_1 0x2701
|
|
#define SPR_MPL_WORLD_ACCESS_SET_2 0x2702
|
|
#define SPR_PASS 0x2709
|
|
#define SPR_PERF_COUNT_0 0x2005
|
|
#define SPR_PERF_COUNT_1 0x2006
|
|
#define SPR_PERF_COUNT_CTL 0x2007
|
|
#define SPR_PERF_COUNT_DN_CTL 0x2008
|
|
#define SPR_PERF_COUNT_STS 0x2009
|
|
#define SPR_PROC_STATUS 0x2784
|
|
#define SPR_SIM_CONTROL 0x2785
|
|
#define SPR_SINGLE_STEP_CONTROL_0 0x0405
|
|
#define SPR_SINGLE_STEP_CONTROL_0__CANCELED_MASK 0x1
|
|
#define SPR_SINGLE_STEP_CONTROL_0__INHIBIT_MASK 0x2
|
|
#define SPR_SINGLE_STEP_CONTROL_1 0x0305
|
|
#define SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK 0x1
|
|
#define SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK 0x2
|
|
#define SPR_SINGLE_STEP_CONTROL_2 0x0205
|
|
#define SPR_SINGLE_STEP_CONTROL_2__CANCELED_MASK 0x1
|
|
#define SPR_SINGLE_STEP_CONTROL_2__INHIBIT_MASK 0x2
|
|
#define SPR_SINGLE_STEP_EN_0_0 0x250a
|
|
#define SPR_SINGLE_STEP_EN_0_1 0x240a
|
|
#define SPR_SINGLE_STEP_EN_0_2 0x230a
|
|
#define SPR_SINGLE_STEP_EN_1_0 0x250b
|
|
#define SPR_SINGLE_STEP_EN_1_1 0x240b
|
|
#define SPR_SINGLE_STEP_EN_1_2 0x230b
|
|
#define SPR_SINGLE_STEP_EN_2_0 0x250c
|
|
#define SPR_SINGLE_STEP_EN_2_1 0x240c
|
|
#define SPR_SINGLE_STEP_EN_2_2 0x230c
|
|
#define SPR_SYSTEM_SAVE_0_0 0x2582
|
|
#define SPR_SYSTEM_SAVE_0_1 0x2583
|
|
#define SPR_SYSTEM_SAVE_0_2 0x2584
|
|
#define SPR_SYSTEM_SAVE_0_3 0x2585
|
|
#define SPR_SYSTEM_SAVE_1_0 0x2482
|
|
#define SPR_SYSTEM_SAVE_1_1 0x2483
|
|
#define SPR_SYSTEM_SAVE_1_2 0x2484
|
|
#define SPR_SYSTEM_SAVE_1_3 0x2485
|
|
#define SPR_SYSTEM_SAVE_2_0 0x2382
|
|
#define SPR_SYSTEM_SAVE_2_1 0x2383
|
|
#define SPR_SYSTEM_SAVE_2_2 0x2384
|
|
#define SPR_SYSTEM_SAVE_2_3 0x2385
|
|
#define SPR_TILE_COORD 0x270b
|
|
#define SPR_TILE_RTF_HWM 0x270c
|
|
#define SPR_TILE_TIMER_CONTROL 0x1605
|
|
#define SPR_UDN_AVAIL_EN 0x1b05
|
|
#define SPR_UDN_DATA_AVAIL 0x0b80
|
|
#define SPR_UDN_DEADLOCK_TIMEOUT 0x1906
|
|
#define SPR_UDN_DEMUX_COUNT_0 0x0b05
|
|
#define SPR_UDN_DEMUX_COUNT_1 0x0b06
|
|
#define SPR_UDN_DEMUX_COUNT_2 0x0b07
|
|
#define SPR_UDN_DEMUX_COUNT_3 0x0b08
|
|
#define SPR_UDN_DIRECTION_PROTECT 0x1505
|
|
#define SPR_UDN_PENDING 0x0b0a
|
|
#define SPR_WATCH_MASK 0x200a
|
|
#define SPR_WATCH_VAL 0x200b
|
|
|
|
#endif /* !defined(__ARCH_SPR_DEF_64_H__) */
|
|
|
|
#endif /* !defined(__DOXYGEN__) */
|