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5204ea79ea
Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access upper word of extended to 64-bits CP0 registers. In MIPS64, when CP0 destination register specified is the EntryLo0 or EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or EntryLo1. This is to compensate for RI and XI, which were shifted to bits 63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate functions for EntryLo0 and EntryLo1. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> |
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| .. | ||
| cpu-qom.h | ||
| cpu.c | ||
| cpu.h | ||
| dsp_helper.c | ||
| gdbstub.c | ||
| helper.c | ||
| helper.h | ||
| kvm_mips.h | ||
| kvm.c | ||
| lmi_helper.c | ||
| machine.c | ||
| Makefile.objs | ||
| mips-defs.h | ||
| msa_helper.c | ||
| op_helper.c | ||
| TODO | ||
| translate_init.c | ||
| translate.c | ||