mirror of
https://github.com/xemu-project/xemu.git
synced 2024-12-04 09:53:32 +00:00
1602001195
The Aspeed AST2400 integrates a set of 14 I2C/SMBus bus controllers directly connected to the APB bus. They can be programmed as master or slave but the propopsed model only supports the master mode. On the TODO list, we also have : - improve and harden the state machine. - bus recovery support (used by the Linux driver). - transfer mode state machine bits. this is not strictly necessary as it is mostly used for debug. The bus busy bit is deducted from the I2C core engine of qemu. - support of the pool buffer: 2048 bytes of internal SRAM (not used by the Linux driver). Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1464704307-25178-1-git-send-email-clg@kaod.org [PMM: removed unused functions aspeed_i2c_bus_get_state() and aspeed_i2c_bus_set_state()] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
63 lines
1.6 KiB
C
63 lines
1.6 KiB
C
/*
|
|
* ASPEED AST2400 I2C Controller
|
|
*
|
|
* Copyright (C) 2016 IBM Corp.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
* (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License along
|
|
* with this program; if not, write to the Free Software Foundation, Inc.,
|
|
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
|
*/
|
|
#ifndef ASPEED_I2C_H
|
|
#define ASPEED_I2C_H
|
|
|
|
#include "hw/i2c/i2c.h"
|
|
|
|
#define TYPE_ASPEED_I2C "aspeed.i2c"
|
|
#define ASPEED_I2C(obj) \
|
|
OBJECT_CHECK(AspeedI2CState, (obj), TYPE_ASPEED_I2C)
|
|
|
|
#define ASPEED_I2C_NR_BUSSES 14
|
|
|
|
struct AspeedI2CState;
|
|
|
|
typedef struct AspeedI2CBus {
|
|
struct AspeedI2CState *controller;
|
|
|
|
MemoryRegion mr;
|
|
|
|
I2CBus *bus;
|
|
uint8_t id;
|
|
|
|
uint32_t ctrl;
|
|
uint32_t timing[2];
|
|
uint32_t intr_ctrl;
|
|
uint32_t intr_status;
|
|
uint32_t cmd;
|
|
uint32_t buf;
|
|
} AspeedI2CBus;
|
|
|
|
typedef struct AspeedI2CState {
|
|
SysBusDevice parent_obj;
|
|
|
|
MemoryRegion iomem;
|
|
qemu_irq irq;
|
|
|
|
uint32_t intr_status;
|
|
|
|
AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES];
|
|
} AspeedI2CState;
|
|
|
|
I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr);
|
|
|
|
#endif /* ASPEED_I2C_H */
|