xemu/target/ppc
Gustavo Romero 565cb10967 target/ppc: add user read/write functions for MMCR0
Userspace need access to PMU SPRs to be able to operate the PMU. One of
such SPRs is MMCR0.

MMCR0, as defined by PowerISA v3.1, is classified as a 'group A' PMU
register. This class of registers has common read/write rules that are
governed by MMCR0 PMCC bits. MMCR0 is also not fully exposed to problem
state: only MMCR0_FC, MMCR0_PMAO and MMCR0_PMAE bits are
readable/writable in this case.

This patch exposes MMCR0 to userspace by doing the following:

- two new callbacks, spr_read_MMCR0_ureg() and spr_write_MMCR0_ureg(),
are added to be used as problem state read/write callbacks of UMMCR0.
Both callbacks filters the amount of bits userspace is able to
read/write by using a MMCR0_UREG_MASK;

- problem state access control is done by the spr_groupA_read_allowed()
and spr_groupA_write_allowed() helpers. These helpers will read the
current PMCC bits from DisasContext and check whether the read/write
MMCR0 operation is valid or noti;

- to avoid putting exclusive PMU logic into the already loaded
translate.c file, let's create a new 'power8-pmu-regs.c.inc' file that
will hold all the spr_read/spr_write functions of PMU registers.

The 'power8' name of this new file intends to hint about the proven
support of the PMU logic to be added. The code has been tested with the
IBM POWER chip family, POWER8 being the oldest version tested. This
doesn't mean that the PMU logic will break with any other PPC64 chip
that implements Book3s, but rather that we can't assert that it works
properly with any Book3s compliant chip.

CC: Gustavo Romero <gustavo.romero@linaro.org>
Signed-off-by: Gustavo Romero <gromero@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211018010133.315842-3-danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-10-21 11:42:47 +11:00
..
translate target/ppc: Ease L=0 requirement on cmp/cmpi/cmpl/cmpli for ppc32 2021-07-29 10:59:49 +10:00
arch_dump.c target/ppc: Introduce ppc_interrupts_little_endian() 2021-07-09 10:38:18 +10:00
compat.c
cpu_init.c target/ppc: add user read/write functions for MMCR0 2021-10-21 11:42:47 +11:00
cpu-models.c ppc: Add a POWER10 DD2 CPU 2021-08-27 12:41:13 +10:00
cpu-models.h ppc: Add a POWER10 DD2 CPU 2021-08-27 12:41:13 +10:00
cpu-param.h
cpu-qom.h target/ppc: Remove PowerPCCPUClass.handle_mmu_fault 2021-07-09 10:38:18 +10:00
cpu.c linux-user: Fix XER access in ppc version of elf_core_copy_regs 2021-10-21 11:42:47 +11:00
cpu.h target/ppc: add user read/write functions for MMCR0 2021-10-21 11:42:47 +11:00
dfp_helper.c
excp_helper.c target/ppc: Convert debug to trace events (exceptions) 2021-09-30 12:26:06 +10:00
fpu_helper.c target/ppc: overhauled and moved logic of storing fpscr 2021-06-03 18:10:31 +10:00
gdbstub.c target/ppc: Fix XER access in gdbstub 2021-10-21 11:42:47 +11:00
helper_regs.c target/ppc: add MMCR0 PMCC bits to hflags 2021-10-21 11:42:47 +11:00
helper_regs.h target/ppc: Remove env->immu_idx and env->dmmu_idx 2021-05-04 11:41:25 +10:00
helper.h tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode 2021-06-19 08:51:11 -07:00
insn32.decode target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree 2021-06-03 18:10:31 +10:00
insn64.decode target/ppc: Implement prefixed integer store instructions 2021-06-03 18:10:31 +10:00
int_helper.c target/ppc: fix setting of CR flags in bcdcfsq 2021-09-29 19:37:39 +10:00
internal.h hw/core: Make do_unaligned_access noreturn 2021-09-21 19:36:44 -07:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
kvm_ppc.h target/ppc: Support for H_RPT_INVALIDATE hcall 2021-07-09 11:01:06 +10:00
kvm-stub.c
kvm.c target/ppc: Support for H_RPT_INVALIDATE hcall 2021-07-09 11:01:06 +10:00
machine.c target/ppc: updated vscr manipulation in machine.c 2021-05-19 10:30:28 +10:00
mem_helper.c accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h 2021-10-13 08:14:54 -07:00
meson.build target/ppc: divided mmu_helper.c in 2 files 2021-08-27 12:41:13 +10:00
mfrom_table_gen.c
mfrom_table.c.inc
misc_helper.c target/ppc: fold ppc_store_ptcr into it's only caller 2021-06-03 13:22:06 +10:00
mmu_common.c target/ppc: moved store_40x_sler to helper_regs.c 2021-08-27 12:41:13 +10:00
mmu_helper.c target/ppc: divided mmu_helper.c in 2 files 2021-08-27 12:41:13 +10:00
mmu-book3s-v3.c target/ppc: Introduce ppc_xlate 2021-07-09 10:38:19 +10:00
mmu-book3s-v3.h target/ppc: introduce mmu-books.h 2021-07-09 10:38:19 +10:00
mmu-books.h target/ppc: introduce mmu-books.h 2021-07-09 10:38:19 +10:00
mmu-hash32.c target/ppc: change ppc_hash32_xlate to use mmu_idx 2021-07-09 10:38:19 +10:00
mmu-hash32.h target/ppc: change ppc_hash32_xlate to use mmu_idx 2021-07-09 10:38:19 +10:00
mmu-hash64.c target/ppc: changed ppc_hash64_xlate to use mmu_idx 2021-07-09 10:38:19 +10:00
mmu-hash64.h target/ppc: changed ppc_hash64_xlate to use mmu_idx 2021-07-09 10:38:19 +10:00
mmu-radix64.c target/ppc: fix address translation bug for radix mmus 2021-07-09 10:38:19 +10:00
mmu-radix64.h target/ppc: fix address translation bug for radix mmus 2021-07-09 10:38:19 +10:00
monitor.c target/ppc: Fix XER access in monitor 2021-10-21 11:42:47 +11:00
power8-pmu-regs.c.inc target/ppc: add user read/write functions for MMCR0 2021-10-21 11:42:47 +11:00
spr_tcg.h target/ppc: add user read/write functions for MMCR0 2021-10-21 11:42:47 +11:00
tcg-stub.c target/ppc: created tcg-stub.c file 2021-06-03 13:22:06 +10:00
timebase_helper.c
trace-events target/ppc: Convert debug to trace events (exceptions) 2021-09-30 12:26:06 +10:00
trace.h
translate.c target/ppc: add user read/write functions for MMCR0 2021-10-21 11:42:47 +11:00
user_only_helper.c