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5c16736a37
Main purpose of this is to delete
*physical = address & 0x1fffffff;
at target-sh4/helper.c:449, using new mmio rule introduced by #5849
This masking is a nice trick to realize P4/A7 duality of SH registers.
But, IMHO, it is logically wrong.
Most of SH4 cpu control registers in P4 area(0xfc000000...0xffffffff) have
one more address called A7 which is usually P4 address with upper 3bits masked.
This is an address only appears in TLB's physical address part.
Current code use trick writing drivers as if they are really in A7
(that's why you see many *_A7 in hw/sh*.c), and using translation P4 to A7.
Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5935 c046a42c-6fe2-441c-8c8c-71466251a162
59 lines
1.7 KiB
C
59 lines
1.7 KiB
C
#ifndef QEMU_SH_H
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#define QEMU_SH_H
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/* Definitions for SH board emulation. */
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#include "sh_intc.h"
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#define A7ADDR(x) ((x) & 0x1fffffff)
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#define P4ADDR(x) ((x) | 0xe0000000)
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/* sh7750.c */
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struct SH7750State;
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struct SH7750State *sh7750_init(CPUState * cpu);
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typedef struct {
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/* The callback will be triggered if any of the designated lines change */
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uint16_t portamask_trigger;
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uint16_t portbmask_trigger;
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/* Return 0 if no action was taken */
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int (*port_change_cb) (uint16_t porta, uint16_t portb,
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uint16_t * periph_pdtra,
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uint16_t * periph_portdira,
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uint16_t * periph_pdtrb,
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uint16_t * periph_portdirb);
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} sh7750_io_device;
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int sh7750_register_io_device(struct SH7750State *s,
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sh7750_io_device * device);
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/* sh_timer.c */
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#define TMU012_FEAT_TOCR (1 << 0)
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#define TMU012_FEAT_3CHAN (1 << 1)
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#define TMU012_FEAT_EXTCLK (1 << 2)
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void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq,
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qemu_irq ch0_irq, qemu_irq ch1_irq,
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qemu_irq ch2_irq0, qemu_irq ch2_irq1);
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/* sh_serial.c */
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#define SH_SERIAL_FEAT_SCIF (1 << 0)
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void sh_serial_init (target_phys_addr_t base, int feat,
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uint32_t freq, CharDriverState *chr,
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qemu_irq eri_source,
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qemu_irq rxi_source,
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qemu_irq txi_source,
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qemu_irq tei_source,
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qemu_irq bri_source);
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/* sh7750.c */
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qemu_irq sh7750_irl(struct SH7750State *s);
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/* tc58128.c */
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int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2);
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/* ide.c */
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void mmio_ide_init(target_phys_addr_t membase, target_phys_addr_t membase2,
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qemu_irq irq, int shift,
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BlockDriverState *hd0, BlockDriverState *hd1);
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#endif
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