Paul Burton 62be393423 hw: xilinx-pcie: Add support for Xilinx AXI PCIe Controller ...

Add support for emulating the Xilinx AXI Root Port Bridge for PCI
Express as described by Xilinx' PG055 document. This is a PCIe
controller that can be used with certain series of Xilinx FPGAs, and is
used on the MIPS Boston board which will make use of this code.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[yongbok.kim@imgtec.com:
  removed returning on !level,
  updated IRQ connection with GPIO logic,
  moved xilinx_pcie_init() to boston.c
  replaced stw_le_p() with pci_set_word()
  and other cosmetic changes]
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>

2017-02-21 23:49:29 +00:00

..

apb.c

apb: convert init to realize

2016-07-29 00:07:09 +03:00

bonito.c

pci: Clean up includes

2016-01-29 15:07:24 +00:00

gpex.c

pci: Clean up includes

2016-01-29 15:07:24 +00:00

grackle.c

hw/grackle: fix PCI bus initialization

2016-07-20 19:30:26 +03:00

Makefile.objs

hw: xilinx-pcie: Add support for Xilinx AXI PCIe Controller

2017-02-21 23:49:29 +00:00

pam.c

x86: Clean up includes

2016-01-29 15:07:22 +00:00

piix.c

range: Eliminate direct Range member access

2016-07-04 16:49:33 +03:00

ppce500.c

pci: Clean up includes

2016-01-29 15:07:24 +00:00

prep.c

hw/prep: realize the PCI root bus as part of the prep init

2016-07-20 19:30:26 +03:00

q35.c

range: Eliminate direct Range member access

2016-07-04 16:49:33 +03:00

uninorth.c

ppc: Make uninorth interrupt swizzling identical to Grackle

2016-11-23 12:00:48 +11:00

versatile.c

hw/versatile: realize the PCI root bus as part of the versatile init

2016-07-20 19:30:27 +03:00

xilinx-pcie.c

hw: xilinx-pcie: Add support for Xilinx AXI PCIe Controller

2017-02-21 23:49:29 +00:00