Peter Maydell 62c0ac5041 Adjust types for some memory access functions. ... Reduce inclusion of tcg headers. Fix watchpoints vs replay. Fix tcg/aarch64 roli expansion. Introduce SysemuCPUOps structure. -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmCu3TodHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9ibwf+IyI2B3CrrJUkyzdg AiKasEQJS7XoKRf924THegSHQEzFltDEuOiSdq3x2oFB9iMuZeu/HH/CLdw3qCFb IZgsFhhYRjtzO6aVanyNWE2/b3HViGPI4rRvk09YaQg+FEEKqCw6Qb+MM3yv9Aa2 7VGsYX1u0RK/W6CfgUFULcnjbKUcPtOnZRZZMiNKwA6Jg9m19ASAVuLCmoQrcIg7 PrpGUuSn8VrC3ICGcqALbCVp+HWcMERuckAlSJ3cOvAng+vcvxSy8lkUm5sibkm2 27k+t2IzwTObVlyVKj2TvLC3GVXHg/0juXg7UH1h1+cshn0BIX5HuzDU8NyMj+Dj RHeoqA== =RPLq -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210526' into staging Adjust types for some memory access functions. Reduce inclusion of tcg headers. Fix watchpoints vs replay. Fix tcg/aarch64 roli expansion. Introduce SysemuCPUOps structure. # gpg: Signature made Thu 27 May 2021 00:43:54 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210526: (31 commits) hw/core: Constify TCGCPUOps target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps cpu: Move CPUClass::write_elf* to SysemuCPUOps cpu: Move CPUClass::get_crash_info to SysemuCPUOps cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps cpu: Move CPUClass::vmsd to SysemuCPUOps cpu: Introduce SysemuCPUOps structure cpu: Move AVR target vmsd field from CPUClass to DeviceClass cpu: Rename CPUClass vmsd -> legacy_vmsd cpu: Assert DeviceClass::vmsd is NULL on user emulation cpu: Directly use get_memory_mapping() fallback handlers in place cpu: Directly use get_paging_enabled() fallback handlers in place cpu: Directly use cpu_write_elf*() fallback handlers in place cpu: Introduce cpu_virtio_is_big_endian() cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs cpu: Split as cpu-common / cpu-sysemu ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2021-05-28 16:25:21 +01:00
..
cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 07:03:34 -07:00
cpu-qom.h	qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros	2020-09-18 14:12:32 -04:00
cpu.c	hw/core: Constify TCGCPUOps	2021-05-26 15:33:59 -07:00
cpu.h	target/m68k: implement m68k "any instruction" trace mode	2021-05-26 20:45:18 +02:00
fpu_helper.c	target/m68k: Add vmstate definition for M68kCPU	2020-12-12 18:12:39 +01:00
gdbstub.c	gdbstub: extend GByteArray to read register helpers	2020-03-17 17:38:38 +00:00
helper.c	target/m68k: Drop use of gdb_get_float64() and ldfq_p()	2021-02-15 09:38:40 +00:00
helper.h	target/m68k: implement opcode fetoxm1	2020-06-02 13:59:02 +02:00
m68k-semi.c	gdbstub: drop CPUEnv from gdb_exit()	2021-01-18 10:05:06 +00:00
meson.build	meson: target	2020-08-21 06:30:35 -04:00
monitor.c	hmp: Pass monitor to mon_get_cpu_env()	2020-11-13 12:45:51 +00:00
op_helper.c	Prepare MacOS ROM support:	2021-03-12 18:56:56 +00:00
qregs.def	target-m68k: use floatx80 internally	2017-06-21 22:10:29 +02:00
softfloat_fpsp_tables.h	m68k comments break patch submission due to being incorrectly formatted	2019-06-26 17:14:39 +02:00
softfloat.c	softfloat: merge floatx80_mod and floatx80_rem	2020-06-26 09:39:37 -04:00
softfloat.h	softfloat: merge floatx80_mod and floatx80_rem	2020-06-26 09:39:37 -04:00
translate.c	target/m68k: implement m68k "any instruction" trace mode	2021-05-26 20:45:18 +02:00