Benjamin Herrenschmidt 68d45bb61c tcg/ppc: Improve unaligned load/store handling on 64-bit backend ... Currently, we get to the slow path for any unaligned access in the backend, because we effectively preserve the bottom address bits below the alignment requirement when comparing with the TLB entry, so any non-0 bit there will cause the compare to fail. For the same number of instructions, we can instead add the access size - 1 to the address and stick to clearing all the bottom bits. That means that normal unaligned accesses will not fallback (the HW will handle them fine). Only when crossing a page boundary well we end up having a mismatch because we'll end up pointing to the next page which cannot possibly be in that same TLB entry. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Message-Id: <1437455978.5809.2.camel@kernel.crashing.org> Signed-off-by: Richard Henderson <rth@twiddle.net>		2015-08-24 11:10:54 -07:00
..
tcg-target.c	tcg/ppc: Improve unaligned load/store handling on 64-bit backend	2015-08-24 11:10:54 -07:00
tcg-target.h	tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32	2015-08-24 11:10:54 -07:00