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10fb1340b1
Since cpu_check_irqs() doesn't reference to anything outside of CPUSPARCState, it better belongs to the architectural code in target/, rather than the hardware specific code in hw/. Note: while we moved the trace events, we don't rename them. Remark: this allows us to build the leon3 machine stand alone, fixing this link failure (because cpu_check_irqs is defined in hw/sparc/sun4m.c which is only built when CONFIG_SUN4M is selected): /usr/bin/ld: target_sparc_win_helper.c.o: in function `cpu_put_psr': target/sparc/win_helper.c:91: undefined reference to `cpu_check_irqs' Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210428141655.387430-5-f4bug@amsat.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
172 lines
5.4 KiB
C
172 lines
5.4 KiB
C
/*
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* Sparc32 interrupt helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "cpu.h"
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#include "trace.h"
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#include "exec/log.h"
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#include "sysemu/runstate.h"
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static const char * const excp_names[0x80] = {
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[TT_TFAULT] = "Instruction Access Fault",
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[TT_ILL_INSN] = "Illegal Instruction",
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[TT_PRIV_INSN] = "Privileged Instruction",
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[TT_NFPU_INSN] = "FPU Disabled",
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[TT_WIN_OVF] = "Window Overflow",
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[TT_WIN_UNF] = "Window Underflow",
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[TT_UNALIGNED] = "Unaligned Memory Access",
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[TT_FP_EXCP] = "FPU Exception",
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[TT_DFAULT] = "Data Access Fault",
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[TT_TOVF] = "Tag Overflow",
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[TT_EXTINT | 0x1] = "External Interrupt 1",
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[TT_EXTINT | 0x2] = "External Interrupt 2",
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[TT_EXTINT | 0x3] = "External Interrupt 3",
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[TT_EXTINT | 0x4] = "External Interrupt 4",
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[TT_EXTINT | 0x5] = "External Interrupt 5",
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[TT_EXTINT | 0x6] = "External Interrupt 6",
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[TT_EXTINT | 0x7] = "External Interrupt 7",
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[TT_EXTINT | 0x8] = "External Interrupt 8",
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[TT_EXTINT | 0x9] = "External Interrupt 9",
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[TT_EXTINT | 0xa] = "External Interrupt 10",
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[TT_EXTINT | 0xb] = "External Interrupt 11",
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[TT_EXTINT | 0xc] = "External Interrupt 12",
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[TT_EXTINT | 0xd] = "External Interrupt 13",
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[TT_EXTINT | 0xe] = "External Interrupt 14",
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[TT_EXTINT | 0xf] = "External Interrupt 15",
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[TT_CODE_ACCESS] = "Instruction Access Error",
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[TT_DATA_ACCESS] = "Data Access Error",
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[TT_DIV_ZERO] = "Division By Zero",
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[TT_NCP_INSN] = "Coprocessor Disabled",
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};
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static const char *excp_name_str(int32_t exception_index)
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{
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if (exception_index < 0 || exception_index >= ARRAY_SIZE(excp_names)) {
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return "Unknown";
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}
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return excp_names[exception_index];
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}
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void cpu_check_irqs(CPUSPARCState *env)
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{
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CPUState *cs;
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/* We should be holding the BQL before we mess with IRQs */
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g_assert(qemu_mutex_iothread_locked());
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if (env->pil_in && (env->interrupt_index == 0 ||
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(env->interrupt_index & ~15) == TT_EXTINT)) {
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unsigned int i;
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for (i = 15; i > 0; i--) {
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if (env->pil_in & (1 << i)) {
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int old_interrupt = env->interrupt_index;
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env->interrupt_index = TT_EXTINT | i;
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if (old_interrupt != env->interrupt_index) {
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cs = env_cpu(env);
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trace_sun4m_cpu_interrupt(i);
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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break;
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}
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}
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} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
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cs = env_cpu(env);
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trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
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env->interrupt_index = 0;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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void sparc_cpu_do_interrupt(CPUState *cs)
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = &cpu->env;
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int cwp, intno = cs->exception_index;
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/* Compute PSR before exposing state. */
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if (env->cc_op != CC_OP_FLAGS) {
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cpu_get_psr(env);
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}
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if (qemu_loglevel_mask(CPU_LOG_INT)) {
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static int count;
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const char *name;
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if (intno < 0 || intno >= 0x100) {
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name = "Unknown";
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} else if (intno >= 0x80) {
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name = "Trap Instruction";
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} else {
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name = excp_name_str(intno);
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}
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qemu_log("%6d: %s (v=%02x)\n", count, name, intno);
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log_cpu_state(cs, 0);
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#if 0
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{
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int i;
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uint8_t *ptr;
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qemu_log(" code=");
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ptr = (uint8_t *)env->pc;
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for (i = 0; i < 16; i++) {
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qemu_log(" %02x", ldub(ptr + i));
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}
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qemu_log("\n");
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}
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#endif
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count++;
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}
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#if !defined(CONFIG_USER_ONLY)
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if (env->psret == 0) {
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if (cs->exception_index == 0x80 &&
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env->def.features & CPU_FEATURE_TA0_SHUTDOWN) {
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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} else {
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cpu_abort(cs, "Trap 0x%02x (%s) while interrupts disabled, "
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"Error state",
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cs->exception_index, excp_name_str(cs->exception_index));
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}
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return;
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}
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#endif
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env->psret = 0;
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cwp = cpu_cwp_dec(env, env->cwp - 1);
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cpu_set_cwp(env, cwp);
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env->regwptr[9] = env->pc;
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env->regwptr[10] = env->npc;
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env->psrps = env->psrs;
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env->psrs = 1;
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env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
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env->pc = env->tbr;
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env->npc = env->pc + 4;
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cs->exception_index = -1;
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#if !defined(CONFIG_USER_ONLY)
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/* IRQ acknowledgment */
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if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) {
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env->qemu_irq_ack(env, env->irq_manager, intno);
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}
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#endif
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}
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