xemu/target-ppc
Madhavan Srinivasan 7624789234 target-ppc/fpu_helper: fix FPSCR_FX bit shift operation
Currently in TCG mode, updating floating exception
summary bit (FPSCR_FX) in fpscr also updates
the upper 32bits of fpscr with all 1s.
Modify the bit shift operation statement to use
1ULL instead.

Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2015-11-30 19:39:01 +11:00
..
2015-01-07 16:16:27 +01:00
2013-07-01 01:11:14 +02:00
2015-11-12 13:15:54 +11:00
2014-03-05 03:06:23 +01:00