xemu/target/arm
Jamie Iles 6e0c60a2be target/arm: fix missing exception class
The DAIF and PAC checks used raise_exception_ra to raise an exception
and unwind CPU state but raise_exception_ra is currently designed for
handling data aborts as the syndrome is partially precomputed and
encoded in the TB and then merged in merge_syn_data_abort when handling
the data abort.  Using raise_exception_ra for DAIF and PAC checks
results in an empty syndrome being retrieved from data[2] in
restore_state_to_opc and setting ESR to 0.  This manifested as:

  kvm [571]: Unknown exception class: esr: 0x000000 –
  Unknown/Uncategorized

when launching a KVM guest when the host qemu used a CPU supporting
EL2+pointer authentication and enabling pointer authentication in the
guest.

Rework raise_exception_ra such that the state is restored before raising
the exception so that the exception is not clobbered by
restore_state_to_opc.

Fixes: 0d43e1a2d2 ("target/arm: Add PAuth helpers")
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jamie Iles <jamie@nuviainc.com>
[PMM: added comment]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-06-03 16:43:25 +01:00
..
a32-uncond.decode
a32.decode
arch_dump.c
arm_ldst.h
arm-powerctl.c
arm-powerctl.h
cpu64.c target/arm: Enable SVE2 and related extensions 2021-05-25 16:01:44 +01:00
cpu_tcg.c hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
cpu-param.h
cpu-qom.h
cpu.c target/arm: Allow board models to specify initial NS VTOR 2021-06-03 16:43:25 +01:00
cpu.h target/arm: Allow board models to specify initial NS VTOR 2021-06-03 16:43:25 +01:00
crypto_helper.c
debug_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c target/arm: Add wrapper macros for accessing tbflags 2021-04-30 11:16:50 +01:00
helper-a64.h target/arm: Merge mte_check1, mte_checkN 2021-04-30 11:16:49 +01:00
helper-sve.h target/arm: Implement SVE2 bitwise shift immediate 2021-05-25 16:01:44 +01:00
helper.c target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 2021-05-25 16:01:43 +01:00
helper.h target/arm: Implement integer matrix multiply accumulate 2021-05-25 16:01:44 +01:00
idau.h
internals.h target/arm: Rename mte_probe1 to mte_probe 2021-04-30 11:16:49 +01:00
iwmmxt_helper.c
kvm64.c target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 2021-05-25 16:01:43 +01:00
kvm_arm.h hw/arm/virt: KVM: The IPA lower bound is 32 2021-03-12 12:47:11 +00:00
kvm-consts.h
kvm-stub.c
kvm.c hw/arm/virt: KVM: The IPA lower bound is 32 2021-03-12 12:47:11 +00:00
m_helper.c target/arm: Use correct SP in M-profile exception return 2021-05-25 16:01:43 +01:00
m-nocp.decode
machine.c target/arm: Make FPSCR.LTPSIZE writable for MVE 2021-06-03 16:43:25 +01:00
meson.build target/arm: Make translate-neon.c.inc its own compilation unit 2021-05-10 13:24:09 +01:00
monitor.c
mte_helper.c target/arm: Rename mte_probe1 to mte_probe 2021-04-30 11:16:49 +01:00
neon_helper.c target/arm: Split out saturating/rounding shifts from neon 2021-05-25 16:01:43 +01:00
neon-dp.decode
neon-ls.decode target/arm: Fix decode of align in VLDST_single 2021-04-30 11:16:49 +01:00
neon-shared.decode target/arm: Implement integer matrix multiply accumulate 2021-05-25 16:01:44 +01:00
op_addsub.h
op_helper.c target/arm: fix missing exception class 2021-06-03 16:43:25 +01:00
pauth_helper.c
psci.c
sve_helper.c target/arm: Move endian adjustment macros to vec_internal.h 2021-05-25 16:01:44 +01:00
sve.decode target/arm: Implement integer matrix multiply accumulate 2021-05-25 16:01:44 +01:00
syndrome.h
t16.decode
t32.decode
tlb_helper.c target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fill 2021-03-23 14:07:55 +00:00
trace-events docs: fix references to docs/devel/tracing.rst 2021-06-02 06:51:09 +02:00
trace.h
translate-a32.h target/arm: Make translate-neon.c.inc its own compilation unit 2021-05-10 13:24:09 +01:00
translate-a64.c target/arm: Mark LDS{MIN,MAX} as signed operations 2021-06-03 16:43:25 +01:00
translate-a64.h target/arm: Implement SVE2 XAR 2021-05-25 16:01:44 +01:00
translate-m-nocp.c target/arm: Split m-nocp trans functions into their own file 2021-05-10 13:24:09 +01:00
translate-neon.c target/arm: Implement integer matrix multiply accumulate 2021-05-25 16:01:44 +01:00
translate-sve.c target/arm: Implement integer matrix multiply accumulate 2021-05-25 16:01:44 +01:00
translate-vfp.c target/arm: Implement M-profile VPR register 2021-06-03 16:43:25 +01:00
translate.c target/arm: Make sure that commpage's tb->size != 0 2021-05-20 14:19:30 +02:00
translate.h target/arm: Move NeonGenThreeOpEnvFn typedef to translate.h 2021-05-10 13:24:09 +01:00
vec_helper.c target/arm: Implement integer matrix multiply accumulate 2021-05-25 16:01:44 +01:00
vec_internal.h target/arm: Move endian adjustment macros to vec_internal.h 2021-05-25 16:01:44 +01:00
vfp_helper.c target/arm: Make FPSCR.LTPSIZE writable for MVE 2021-06-03 16:43:25 +01:00
vfp-uncond.decode
vfp.decode