xemu/target-tricore
Richard Henderson 42a268c241 tcg: Change translator-side labels to a pointer
This is improved type checking for the translators -- it's no longer
possible to accidentally swap arguments to the branch functions.

Note that the code generating backends still manipulate labels as int.

With notable exceptions, the scope of the change is just a few lines
for each target, so it's not worth building extra machinery to do this
change in per-target increments.

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Leon Alrae <leon.alrae@imgtec.com>
Cc: Anthony Green <green@moxielogic.com>
Cc: Jia Liu <proljc@gmail.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Blue Swirl <blauwirbel@gmail.com>
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-03-13 12:28:18 -07:00
..
cpu-qom.h target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
cpu.c target-tricore: Several translator and cpu model fixes 2015-01-26 19:56:45 +00:00
cpu.h cpu: Make cpu_init() return QOM CPUState object 2015-03-10 17:33:51 +01:00
csfr.def target-tricore: Fix new typos 2015-01-15 10:44:13 +03:00
helper.c target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
helper.h target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as first opcode 2015-03-03 01:06:00 +00:00
Makefile.objs
op_helper.c target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as first opcode 2015-03-03 01:06:00 +00:00
translate.c tcg: Change translator-side labels to a pointer 2015-03-13 12:28:18 -07:00
tricore-defs.h
tricore-opcodes.h target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as first opcode 2015-03-03 01:05:44 +00:00