xemu-project/xemu
1
0
Fork 0
mirror of https://github.com/xemu-project/xemu.git synced 2024-11-27 21:40:49 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
6e7cd94462
xemu/target-tricore
History
Paolo Bonzini 5f37fd8e29 target-tricore: fix depositing bits from PCXI into ICR 
Spotted by Coverity, because (env->PCXI & MASK_PCXI_PCPN) >> 24
is always zero.  The immediately preceding assignment is also
wrong though.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <1435147270-1040-1-git-send-email-pbonzini@redhat.com>
2015-06-29 14:02:58 +02:00
..
cpu-qom.h target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
cpu.c target-tricore: introduce ISA v1.6.1 feature 2015-05-22 17:02:33 +02:00
cpu.h target-tricore: introduce ISA v1.6.1 feature 2015-05-22 17:02:33 +02:00
csfr.def target-tricore: Fix new typos 2015-01-15 10:44:13 +03:00
helper.c target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
helper.h target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA 2015-05-22 17:02:34 +02:00
Makefile.objs target-tricore: Add target stubs and qom-cpu 2014-09-01 14:49:20 +01:00
op_helper.c target-tricore: fix depositing bits from PCXI into ICR 2015-06-29 14:02:58 +02:00
translate.c disas: Remove uses of CPU env 2015-06-22 17:40:01 +02:00
tricore-defs.h target-tricore: Add target stubs and qom-cpu 2014-09-01 14:49:20 +01:00
tricore-opcodes.h target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA 2015-05-22 17:02:34 +02:00