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https://github.com/xemu-project/xemu.git
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551bd27f22
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4840 c046a42c-6fe2-441c-8c8c-71466251a162
421 lines
14 KiB
C
421 lines
14 KiB
C
/*
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* internal execution defines for qemu
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* allow to see translation results - the slowdown should be negligible, so we leave it */
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#define DEBUG_DISAS
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/* is_jmp field values */
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#define DISAS_NEXT 0 /* next instruction can be analyzed */
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#define DISAS_JUMP 1 /* only pc was modified dynamically */
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#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
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#define DISAS_TB_JUMP 3 /* only pc was modified statically */
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typedef struct TranslationBlock TranslationBlock;
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/* XXX: make safe guess about sizes */
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#define MAX_OP_PER_INSTR 64
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/* A Call op needs up to 6 + 2N parameters (N = number of arguments). */
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#define MAX_OPC_PARAM 10
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#define OPC_BUF_SIZE 512
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#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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/* Maximum size a TCG op can expand to. This is complicated because a
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single op may require several host instructions and regirster reloads.
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For now take a wild guess at 128 bytes, which should allow at least
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a couple of fixup instructions per argument. */
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#define TCG_MAX_OP_SIZE 128
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#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
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extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
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extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
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extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
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extern target_ulong gen_opc_jump_pc[2];
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extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
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typedef void (GenOpFunc)(void);
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typedef void (GenOpFunc1)(long);
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typedef void (GenOpFunc2)(long, long);
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typedef void (GenOpFunc3)(long, long, long);
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extern FILE *logfile;
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extern int loglevel;
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int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
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int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
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void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
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unsigned long searched_pc, int pc_pos, void *puc);
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unsigned long code_gen_max_block_size(void);
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void cpu_gen_init(void);
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int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
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int *gen_code_size_ptr);
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int cpu_restore_state(struct TranslationBlock *tb,
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CPUState *env, unsigned long searched_pc,
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void *puc);
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int cpu_restore_state_copy(struct TranslationBlock *tb,
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CPUState *env, unsigned long searched_pc,
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void *puc);
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void cpu_resume_from_signal(CPUState *env1, void *puc);
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void cpu_io_recompile(CPUState *env, void *retaddr);
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TranslationBlock *tb_gen_code(CPUState *env,
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target_ulong pc, target_ulong cs_base, int flags,
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int cflags);
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void cpu_exec_init(CPUState *env);
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int page_unprotect(target_ulong address, unsigned long pc, void *puc);
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void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
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int is_cpu_write_access);
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void tb_invalidate_page_range(target_ulong start, target_ulong end);
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void tlb_flush_page(CPUState *env, target_ulong addr);
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void tlb_flush(CPUState *env, int flush_global);
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int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
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target_phys_addr_t paddr, int prot,
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int mmu_idx, int is_softmmu);
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static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
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target_phys_addr_t paddr, int prot,
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int mmu_idx, int is_softmmu)
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{
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if (prot & PAGE_READ)
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prot |= PAGE_EXEC;
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return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
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}
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#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
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#define CODE_GEN_PHYS_HASH_BITS 15
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#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
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#define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
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/* estimated block size for TB allocation */
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/* XXX: use a per code average code fragment size and modulate it
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according to the host CPU */
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#if defined(CONFIG_SOFTMMU)
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#define CODE_GEN_AVG_BLOCK_SIZE 128
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#else
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#define CODE_GEN_AVG_BLOCK_SIZE 64
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#endif
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#if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__)
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#define USE_DIRECT_JUMP
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#endif
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#if defined(__i386__) && !defined(_WIN32)
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#define USE_DIRECT_JUMP
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#endif
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struct TranslationBlock {
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target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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target_ulong cs_base; /* CS base for this block */
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uint64_t flags; /* flags defining in which context the code was generated */
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uint16_t size; /* size of target code for this block (1 <=
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size <= TARGET_PAGE_SIZE) */
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uint16_t cflags; /* compile flags */
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#define CF_COUNT_MASK 0x7fff
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#define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
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uint8_t *tc_ptr; /* pointer to the translated code */
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/* next matching tb for physical address. */
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struct TranslationBlock *phys_hash_next;
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/* first and second physical page containing code. The lower bit
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of the pointer tells the index in page_next[] */
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struct TranslationBlock *page_next[2];
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target_ulong page_addr[2];
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/* the following data are used to directly call another TB from
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the code of this one. */
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uint16_t tb_next_offset[2]; /* offset of original jump target */
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#ifdef USE_DIRECT_JUMP
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uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
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#else
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unsigned long tb_next[2]; /* address of jump generated code */
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#endif
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/* list of TBs jumping to this one. This is a circular list using
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the two least significant bits of the pointers to tell what is
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the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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jmp_first */
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struct TranslationBlock *jmp_next[2];
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struct TranslationBlock *jmp_first;
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uint32_t icount;
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};
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static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
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{
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target_ulong tmp;
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tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
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return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
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}
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static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
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{
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target_ulong tmp;
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tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
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return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
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| (tmp & TB_JMP_ADDR_MASK));
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}
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static inline unsigned int tb_phys_hash_func(unsigned long pc)
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{
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return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
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}
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TranslationBlock *tb_alloc(target_ulong pc);
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void tb_free(TranslationBlock *tb);
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void tb_flush(CPUState *env);
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void tb_link_phys(TranslationBlock *tb,
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target_ulong phys_pc, target_ulong phys_page2);
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void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr);
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extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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extern uint8_t *code_gen_ptr;
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extern int code_gen_max_blocks;
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#if defined(USE_DIRECT_JUMP)
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#if defined(__powerpc__)
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static inline void flush_icache_range(unsigned long start, unsigned long stop);
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static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
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{
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/* This must be in concord with INDEX_op_goto_tb inside tcg_out_op */
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uint32_t *ptr;
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long disp = addr - jmp_addr;
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unsigned long patch_size;
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ptr = (uint32_t *)jmp_addr;
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if ((disp << 6) >> 6 != disp) {
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ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */
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ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */
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ptr[2] = 0x7c0903a6; /* mtctr 0 */
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ptr[3] = 0x4e800420; /* brctr */
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patch_size = 16;
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} else {
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/* patch the branch destination */
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if (disp != 16) {
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*ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */
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patch_size = 4;
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} else {
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ptr[0] = 0x60000000; /* nop */
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ptr[1] = 0x60000000;
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ptr[2] = 0x60000000;
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ptr[3] = 0x60000000;
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patch_size = 16;
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}
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}
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/* flush icache */
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flush_icache_range(jmp_addr, jmp_addr + patch_size);
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}
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#elif defined(__i386__) || defined(__x86_64__)
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static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
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{
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/* patch the branch destination */
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*(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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/* no need to flush icache explicitly */
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}
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#elif defined(__arm__)
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static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
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{
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register unsigned long _beg __asm ("a1");
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register unsigned long _end __asm ("a2");
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register unsigned long _flg __asm ("a3");
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/* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
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*(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff;
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/* flush icache */
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_beg = jmp_addr;
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_end = jmp_addr + 4;
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_flg = 0;
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__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
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}
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#endif
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static inline void tb_set_jmp_target(TranslationBlock *tb,
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int n, unsigned long addr)
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{
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unsigned long offset;
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offset = tb->tb_jmp_offset[n];
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tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
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offset = tb->tb_jmp_offset[n + 2];
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if (offset != 0xffff)
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tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
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}
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#else
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/* set the jump target */
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static inline void tb_set_jmp_target(TranslationBlock *tb,
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int n, unsigned long addr)
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{
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tb->tb_next[n] = addr;
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}
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#endif
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static inline void tb_add_jump(TranslationBlock *tb, int n,
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TranslationBlock *tb_next)
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{
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/* NOTE: this test is only needed for thread safety */
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if (!tb->jmp_next[n]) {
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/* patch the native jump address */
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tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
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/* add in TB jmp circular list */
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tb->jmp_next[n] = tb_next->jmp_first;
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tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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}
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}
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TranslationBlock *tb_find_pc(unsigned long pc_ptr);
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#ifndef offsetof
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#define offsetof(type, field) ((size_t) &((type *)0)->field)
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#endif
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#if defined(_WIN32)
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#define ASM_DATA_SECTION ".section \".data\"\n"
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#define ASM_PREVIOUS_SECTION ".section .text\n"
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#elif defined(__APPLE__)
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#define ASM_DATA_SECTION ".data\n"
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#define ASM_PREVIOUS_SECTION ".text\n"
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#else
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#define ASM_DATA_SECTION ".section \".data\"\n"
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#define ASM_PREVIOUS_SECTION ".previous\n"
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#endif
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#define ASM_OP_LABEL_NAME(n, opname) \
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ASM_NAME(__op_label) #n "." ASM_NAME(opname)
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extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
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extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
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extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
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#include "qemu-lock.h"
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extern spinlock_t tb_lock;
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extern int tb_invalidated_flag;
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#if !defined(CONFIG_USER_ONLY)
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void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
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void *retaddr);
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#define ACCESS_TYPE (NB_MMU_MODES + 1)
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#define MEMSUFFIX _code
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#define env cpu_single_env
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#define DATA_SIZE 1
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#include "softmmu_header.h"
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#define DATA_SIZE 2
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#include "softmmu_header.h"
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#define DATA_SIZE 4
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#include "softmmu_header.h"
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#define DATA_SIZE 8
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#include "softmmu_header.h"
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#undef ACCESS_TYPE
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#undef MEMSUFFIX
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#undef env
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#endif
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#if defined(CONFIG_USER_ONLY)
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static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
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{
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return addr;
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}
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#else
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/* NOTE: this function can trigger an exception */
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/* NOTE2: the returned address is not exactly the physical address: it
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is the offset relative to phys_ram_base */
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static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
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{
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int mmu_idx, page_index, pd;
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page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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mmu_idx = cpu_mmu_index(env1);
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if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
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(addr & TARGET_PAGE_MASK))) {
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ldub_code(addr);
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}
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pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
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if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
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#if defined(TARGET_SPARC) || defined(TARGET_MIPS)
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do_unassigned_access(addr, 0, 1, 0);
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#else
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cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
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#endif
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}
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return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base;
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}
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/* Deterministic execution requires that IO only be performed on the last
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instruction of a TB so that interrupts take effect immediately. */
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static inline int can_do_io(CPUState *env)
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{
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if (!use_icount)
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return 1;
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/* If not executing code then assume we are ok. */
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if (!env->current_tb)
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return 1;
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return env->can_do_io != 0;
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}
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#endif
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#ifdef USE_KQEMU
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#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
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#define MSR_QPI_COMMBASE 0xfabe0010
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int kqemu_init(CPUState *env);
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int kqemu_cpu_exec(CPUState *env);
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void kqemu_flush_page(CPUState *env, target_ulong addr);
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void kqemu_flush(CPUState *env, int global);
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void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
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void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
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void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size,
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ram_addr_t phys_offset);
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void kqemu_cpu_interrupt(CPUState *env);
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void kqemu_record_dump(void);
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extern uint32_t kqemu_comm_base;
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static inline int kqemu_is_ok(CPUState *env)
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{
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return(env->kqemu_enabled &&
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(env->cr[0] & CR0_PE_MASK) &&
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!(env->hflags & HF_INHIBIT_IRQ_MASK) &&
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(env->eflags & IF_MASK) &&
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!(env->eflags & VM_MASK) &&
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(env->kqemu_enabled == 2 ||
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((env->hflags & HF_CPL_MASK) == 3 &&
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(env->eflags & IOPL_MASK) != IOPL_MASK)));
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}
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#endif
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