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cb3778a045
The e500 PCI controller has configurable windows that allow a guest OS to selectively map parts of the PCI bus space to CPU address space and to selectively map parts of the CPU address space for DMA requests into PCI visible address ranges. So far, we've simply assumed that this mapping is 1:1 and ignored it. However, the PCICSRBAR (CCSR mapped in PCI bus space) always has to live inside the first 32bits of address space. This means if we always treat all mappings as 1:1, this map will collide with our RAM map from the CPU's point of view. So this patch adds proper ATMU support which allows us to keep the PCICSRBAR below 32bits local to the PCI bus and have another, different window to PCI BARs at the upper end of address space. We leverage this on e500plat though, mpc8544ds stays virtually 1:1 like it was before, but now also goes via ATMU. With this patch, I can run guests with lots of RAM and not coincidently access MSI-X mappings while I really want to access RAM. Signed-off-by: Alexander Graf <agraf@suse.de>
30 lines
692 B
C
30 lines
692 B
C
#ifndef PPCE500_H
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#define PPCE500_H
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#include "hw/boards.h"
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typedef struct PPCE500Params {
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int pci_first_slot;
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int pci_nr_slots;
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/* required -- must at least add toplevel board compatible */
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void (*fixup_devtree)(struct PPCE500Params *params, void *fdt);
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int mpic_version;
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bool has_mpc8xxx_gpio;
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bool has_platform_bus;
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hwaddr platform_bus_base;
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hwaddr platform_bus_size;
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int platform_bus_first_irq;
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int platform_bus_num_irqs;
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hwaddr ccsrbar_base;
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hwaddr pci_pio_base;
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hwaddr pci_mmio_base;
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hwaddr pci_mmio_bus_base;
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hwaddr spin_base;
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} PPCE500Params;
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void ppce500_init(MachineState *machine, PPCE500Params *params);
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#endif
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