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3993c6bddf
For target-mips also change the return type to bool. Make include paths for cpu-qom.h consistent for alpha and unicore32. Signed-off-by: Andreas Färber <afaerber@suse.de> [AF: Updated new target-openrisc function accordingly] Acked-by: Richard Henderson <rth@twiddle.net> (for alpha)
114 lines
2.7 KiB
C
114 lines
2.7 KiB
C
/*
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* QEMU UniCore32 CPU
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*
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* Copyright (c) 2010-2012 Guan Xuetao
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Contributions from 2012-04-01 on are considered under GPL version 2,
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* or (at your option) any later version.
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*/
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#include "cpu.h"
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#include "qemu-common.h"
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static inline void set_feature(CPUUniCore32State *env, int feature)
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{
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env->features |= feature;
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}
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/* CPU models */
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typedef struct UniCore32CPUInfo {
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const char *name;
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void (*instance_init)(Object *obj);
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} UniCore32CPUInfo;
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static void unicore_ii_cpu_initfn(Object *obj)
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{
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UniCore32CPU *cpu = UNICORE32_CPU(obj);
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CPUUniCore32State *env = &cpu->env;
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env->cp0.c0_cpuid = 0x4d000863;
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env->cp0.c0_cachetype = 0x0d152152;
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env->cp0.c1_sys = 0x2000;
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env->cp0.c2_base = 0x0;
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env->cp0.c3_faultstatus = 0x0;
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env->cp0.c4_faultaddr = 0x0;
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env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
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set_feature(env, UC32_HWCAP_CMOV);
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set_feature(env, UC32_HWCAP_UCF64);
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}
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static void uc32_any_cpu_initfn(Object *obj)
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{
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UniCore32CPU *cpu = UNICORE32_CPU(obj);
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CPUUniCore32State *env = &cpu->env;
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env->cp0.c0_cpuid = 0xffffffff;
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env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
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set_feature(env, UC32_HWCAP_CMOV);
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set_feature(env, UC32_HWCAP_UCF64);
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}
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static const UniCore32CPUInfo uc32_cpus[] = {
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{ .name = "UniCore-II", .instance_init = unicore_ii_cpu_initfn },
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{ .name = "any", .instance_init = uc32_any_cpu_initfn },
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};
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static void uc32_cpu_initfn(Object *obj)
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{
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UniCore32CPU *cpu = UNICORE32_CPU(obj);
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CPUUniCore32State *env = &cpu->env;
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cpu_exec_init(env);
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env->cpu_model_str = object_get_typename(obj);
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#ifdef CONFIG_USER_ONLY
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env->uncached_asr = ASR_MODE_USER;
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env->regs[31] = 0;
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#else
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env->uncached_asr = ASR_MODE_PRIV;
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env->regs[31] = 0x03000000;
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#endif
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tlb_flush(env, 1);
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}
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static void uc32_register_cpu_type(const UniCore32CPUInfo *info)
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{
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TypeInfo type_info = {
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.name = info->name,
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.parent = TYPE_UNICORE32_CPU,
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.instance_init = info->instance_init,
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};
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type_register_static(&type_info);
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}
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static const TypeInfo uc32_cpu_type_info = {
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.name = TYPE_UNICORE32_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(UniCore32CPU),
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.instance_init = uc32_cpu_initfn,
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.abstract = true,
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.class_size = sizeof(UniCore32CPUClass),
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};
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static void uc32_cpu_register_types(void)
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{
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int i;
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type_register_static(&uc32_cpu_type_info);
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for (i = 0; i < ARRAY_SIZE(uc32_cpus); i++) {
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uc32_register_cpu_type(&uc32_cpus[i]);
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}
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}
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type_init(uc32_cpu_register_types)
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