Stephen Long 751147928e target/arm: Implement SVE2 SPLICE, EXT ...

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-48-richard.henderson@linaro.org
Message-Id: <20200423180347.9403-1-steplong@quicinc.com>
[rth: Rename the trans_* functions to *_sve2.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

2021-05-25 16:01:44 +01:00

..

alpha

…

arm

target/arm: Implement SVE2 SPLICE, EXT

2021-05-25 16:01:44 +01:00

avr

target/avr: Ignore unimplemented WDR opcode

2021-05-13 19:18:42 +02:00

cris

…

hexagon

…

hppa

…

i386

s390x fixes and cleanups; also related fixes in xtensa,

2021-05-20 18:42:00 +01:00

m68k

…

microblaze

…

mips

target/mips: Set set_default_nan_mode with set_snan_bit_is_one

2021-05-16 07:13:51 -05:00

nios2

…

openrisc

…

ppc

target/ppc: Remove type argument for mmubooke206_get_physical_address

2021-05-19 12:52:07 +10:00

riscv

target/riscv: Fix the RV64H decode comment

2021-05-11 20:02:07 +10:00

rx

…

s390x

target/s390x: Fix translation exception on illegal instruction

2021-05-20 14:19:30 +02:00

sh4

target/sh4: Return error if CPUClass::get_phys_page_debug() fails

2021-05-13 19:00:50 +02:00

sparc

…

tricore

…

xtensa

target/xtensa: clean up unaligned access

2021-05-20 13:02:58 -07:00

meson.build

Drop the deprecated unicore32 target

2021-05-12 18:20:52 +02:00