Richard Henderson 7591db780d target/s390x: Tidy SRST ... Since we require all registers saved on input, read R0 from ENV instead of passing it manually. Recognize the specification exception when R0 contains incorrect data. Keep high bits of result registers unmodified when in 31 or 24-bit mode. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>		2017-07-17 14:13:17 -07:00
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alpha	target/alpha: Use tcg_gen_lookup_and_goto_ptr	2017-06-19 11:11:25 -07:00
arm	target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode	2017-07-11 11:21:26 +01:00
cris	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
hppa	target/hppa: Use tcg_gen_lookup_and_goto_ptr	2017-06-05 09:25:42 -07:00
i386	* gdbstub fixes (Alex)	2017-07-14 12:16:09 +01:00
lm32	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
m68k	target/m68k: add fmovem	2017-06-29 20:29:57 +02:00
microblaze	target-microblaze: Add CPU version 10.0	2017-07-04 09:22:20 +02:00
mips	target/mips: fix msa copy_[s|u]_df rd = 0 corner case	2017-07-11 15:06:34 +01:00
moxie	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
nios2	target/nios2: Fix 64-bit ilp32 compilation	2017-06-05 09:25:42 -07:00
openrisc	target/openrisc: Support non-busy idle state using PMR SPR	2017-05-04 09:39:14 +09:00
ppc	target/ppc: fix CPU hotplug when radix is enabled (TCG)	2017-07-17 15:07:05 +10:00
s390x	target/s390x: Tidy SRST	2017-07-17 14:13:17 -07:00
sh4	target/sh4: fix RTE instruction delay slot	2017-05-30 21:00:56 +02:00
sparc	shutdown: Add source information to SHUTDOWN and RESET	2017-05-23 13:28:17 +02:00
tilegx	migration: Remove unneeded includes of migration/vmstate.h	2017-06-01 18:49:22 +02:00
tricore	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
unicore32	cputlb: drop flush_global flag from tlb_flush	2017-01-13 14:24:37 +00:00
xtensa	char: add backend hotswap handler	2017-07-14 11:04:33 +02:00