Alistair Francis 9b144ed444 hw/riscv: opentitan: Fixup the PLIC context addresses ...

Fixup the PLIC context address to correctly support the threshold and
claim register.

Fixes: ef63100648 ("hw/riscv: opentitan: Update to the latest build")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211025040657.262696-1-alistair.francis@opensource.wdc.com

2021-10-28 14:39:23 +10:00

..

boot.c

hw/riscv: boot: Add a PLIC config string function

2021-10-28 14:39:23 +10:00

Kconfig

hw/intc: Rename sifive_clint sources to riscv_aclint sources

2021-09-21 07:56:49 +10:00

meson.build

hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines

2021-07-20 15:32:49 +02:00

microchip_pfsoc.c

hw/riscv: microchip_pfsoc: Use the PLIC config helper function

2021-10-28 14:39:23 +10:00

numa.c

hw: Do not include qemu/log.h if it is not necessary

2021-05-02 17:24:50 +02:00

opentitan.c

hw/riscv: opentitan: Fixup the PLIC context addresses

2021-10-28 14:39:23 +10:00

riscv_hart.c

hw/riscv: hart: Add a new 'resetvec' property

2020-09-09 15:54:18 -07:00

shakti_c.c

hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id

2021-10-22 23:35:47 +10:00

sifive_e.c

hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id

2021-10-22 23:35:47 +10:00

sifive_u.c

hw/riscv: sifive_u: Use the PLIC config helper function

2021-10-28 14:39:23 +10:00

spike.c

hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id

2021-10-22 23:35:47 +10:00

virt.c

hw/riscv: virt: Use the PLIC config helper function

2021-10-28 14:39:23 +10:00