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https://github.com/xemu-project/xemu.git
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770ae5713a
This patch add support for the LatticeMico32 UART. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
283 lines
17 KiB
Plaintext
283 lines
17 KiB
Plaintext
# Trace events for debugging and performance instrumentation
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#
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# This file is processed by the tracetool script during the build.
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#
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# To add a new trace event:
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#
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# 1. Choose a name for the trace event. Declare its arguments and format
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# string.
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#
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# 2. Call the trace event from code using trace_##name, e.g. multiwrite_cb() ->
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# trace_multiwrite_cb(). The source file must #include "trace.h".
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#
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# Format of a trace event:
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#
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# [disable] <name>(<type1> <arg1>[, <type2> <arg2>] ...) "<format-string>"
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#
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# Example: qemu_malloc(size_t size) "size %zu"
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#
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# The "disable" keyword will build without the trace event.
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# In case of 'simple' trace backend, it will allow the trace event to be
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# compiled, but this would be turned off by default. It can be toggled on via
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# the monitor.
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#
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# The <name> must be a valid as a C function name.
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#
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# Types should be standard C types. Use void * for pointers because the trace
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# system may not have the necessary headers included.
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#
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# The <format-string> should be a sprintf()-compatible format string.
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# qemu-malloc.c
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disable qemu_malloc(size_t size, void *ptr) "size %zu ptr %p"
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disable qemu_realloc(void *ptr, size_t size, void *newptr) "ptr %p size %zu newptr %p"
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disable qemu_free(void *ptr) "ptr %p"
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# osdep.c
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disable qemu_memalign(size_t alignment, size_t size, void *ptr) "alignment %zu size %zu ptr %p"
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disable qemu_vmalloc(size_t size, void *ptr) "size %zu ptr %p"
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disable qemu_vfree(void *ptr) "ptr %p"
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# hw/virtio.c
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disable virtqueue_fill(void *vq, const void *elem, unsigned int len, unsigned int idx) "vq %p elem %p len %u idx %u"
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disable virtqueue_flush(void *vq, unsigned int count) "vq %p count %u"
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disable virtqueue_pop(void *vq, void *elem, unsigned int in_num, unsigned int out_num) "vq %p elem %p in_num %u out_num %u"
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disable virtio_queue_notify(void *vdev, int n, void *vq) "vdev %p n %d vq %p"
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disable virtio_irq(void *vq) "vq %p"
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disable virtio_notify(void *vdev, void *vq) "vdev %p vq %p"
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# block.c
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disable multiwrite_cb(void *mcb, int ret) "mcb %p ret %d"
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disable bdrv_aio_multiwrite(void *mcb, int num_callbacks, int num_reqs) "mcb %p num_callbacks %d num_reqs %d"
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disable bdrv_aio_multiwrite_earlyfail(void *mcb) "mcb %p"
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disable bdrv_aio_multiwrite_latefail(void *mcb, int i) "mcb %p i %d"
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disable bdrv_aio_readv(void *bs, int64_t sector_num, int nb_sectors, void *opaque) "bs %p sector_num %"PRId64" nb_sectors %d opaque %p"
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disable bdrv_aio_writev(void *bs, int64_t sector_num, int nb_sectors, void *opaque) "bs %p sector_num %"PRId64" nb_sectors %d opaque %p"
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# hw/virtio-blk.c
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disable virtio_blk_req_complete(void *req, int status) "req %p status %d"
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disable virtio_blk_rw_complete(void *req, int ret) "req %p ret %d"
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disable virtio_blk_handle_write(void *req, uint64_t sector, size_t nsectors) "req %p sector %"PRIu64" nsectors %zu"
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# posix-aio-compat.c
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disable paio_submit(void *acb, void *opaque, int64_t sector_num, int nb_sectors, int type) "acb %p opaque %p sector_num %"PRId64" nb_sectors %d type %d"
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# ioport.c
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disable cpu_in(unsigned int addr, unsigned int val) "addr %#x value %u"
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disable cpu_out(unsigned int addr, unsigned int val) "addr %#x value %u"
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# balloon.c
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# Since requests are raised via monitor, not many tracepoints are needed.
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disable balloon_event(void *opaque, unsigned long addr) "opaque %p addr %lu"
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# hw/apic.c
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disable apic_local_deliver(int vector, uint32_t lvt) "vector %d delivery mode %d"
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disable apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t vector_num, uint8_t polarity, uint8_t trigger_mode) "dest %d dest_mode %d delivery_mode %d vector %d polarity %d trigger_mode %d"
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disable cpu_set_apic_base(uint64_t val) "%016"PRIx64""
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disable cpu_get_apic_base(uint64_t val) "%016"PRIx64""
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disable apic_mem_readl(uint64_t addr, uint32_t val) "%"PRIx64" = %08x"
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disable apic_mem_writel(uint64_t addr, uint32_t val) "%"PRIx64" = %08x"
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# coalescing
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disable apic_reset_irq_delivered(int apic_irq_delivered) "old coalescing %d"
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disable apic_get_irq_delivered(int apic_irq_delivered) "returning coalescing %d"
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disable apic_set_irq(int apic_irq_delivered) "coalescing %d"
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# hw/cs4231.c
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disable cs4231_mem_readl_dreg(uint32_t reg, uint32_t ret) "read dreg %d: 0x%02x"
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disable cs4231_mem_readl_reg(uint32_t reg, uint32_t ret) "read reg %d: 0x%08x"
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disable cs4231_mem_writel_reg(uint32_t reg, uint32_t old, uint32_t val) "write reg %d: 0x%08x -> 0x%08x"
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disable cs4231_mem_writel_dreg(uint32_t reg, uint32_t old, uint32_t val) "write dreg %d: 0x%02x -> 0x%02x"
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# hw/eccmemctl.c
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disable ecc_mem_writel_mer(uint32_t val) "Write memory enable %08x"
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disable ecc_mem_writel_mdr(uint32_t val) "Write memory delay %08x"
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disable ecc_mem_writel_mfsr(uint32_t val) "Write memory fault status %08x"
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disable ecc_mem_writel_vcr(uint32_t val) "Write slot configuration %08x"
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disable ecc_mem_writel_dr(uint32_t val) "Write diagnostic %08x"
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disable ecc_mem_writel_ecr0(uint32_t val) "Write event count 1 %08x"
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disable ecc_mem_writel_ecr1(uint32_t val) "Write event count 2 %08x"
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disable ecc_mem_readl_mer(uint32_t ret) "Read memory enable %08x"
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disable ecc_mem_readl_mdr(uint32_t ret) "Read memory delay %08x"
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disable ecc_mem_readl_mfsr(uint32_t ret) "Read memory fault status %08x"
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disable ecc_mem_readl_vcr(uint32_t ret) "Read slot configuration %08x"
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disable ecc_mem_readl_mfar0(uint32_t ret) "Read memory fault address 0 %08x"
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disable ecc_mem_readl_mfar1(uint32_t ret) "Read memory fault address 1 %08x"
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disable ecc_mem_readl_dr(uint32_t ret) "Read diagnostic %08x"
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disable ecc_mem_readl_ecr0(uint32_t ret) "Read event count 1 %08x"
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disable ecc_mem_readl_ecr1(uint32_t ret) "Read event count 2 %08x"
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disable ecc_diag_mem_writeb(uint64_t addr, uint32_t val) "Write diagnostic %"PRId64" = %02x"
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disable ecc_diag_mem_readb(uint64_t addr, uint32_t ret) "Read diagnostic %"PRId64"= %02x"
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# hw/lance.c
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disable lance_mem_readw(uint64_t addr, uint32_t ret) "addr=%"PRIx64"val=0x%04x"
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disable lance_mem_writew(uint64_t addr, uint32_t val) "addr=%"PRIx64"val=0x%04x"
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# hw/slavio_intctl.c
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disable slavio_intctl_mem_readl(uint32_t cpu, uint64_t addr, uint32_t ret) "read cpu %d reg 0x%"PRIx64" = %x"
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disable slavio_intctl_mem_writel(uint32_t cpu, uint64_t addr, uint32_t val) "write cpu %d reg 0x%"PRIx64" = %x"
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disable slavio_intctl_mem_writel_clear(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Cleared cpu %d irq mask %x, curmask %x"
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disable slavio_intctl_mem_writel_set(uint32_t cpu, uint32_t val, uint32_t intreg_pending) "Set cpu %d irq mask %x, curmask %x"
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disable slavio_intctlm_mem_readl(uint64_t addr, uint32_t ret) "read system reg 0x%"PRIx64" = %x"
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disable slavio_intctlm_mem_writel(uint64_t addr, uint32_t val) "write system reg 0x%"PRIx64" = %x"
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disable slavio_intctlm_mem_writel_enable(uint32_t val, uint32_t intregm_disabled) "Enabled master irq mask %x, curmask %x"
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disable slavio_intctlm_mem_writel_disable(uint32_t val, uint32_t intregm_disabled) "Disabled master irq mask %x, curmask %x"
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disable slavio_intctlm_mem_writel_target(uint32_t cpu) "Set master irq cpu %d"
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disable slavio_check_interrupts(uint32_t pending, uint32_t intregm_disabled) "pending %x disabled %x"
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disable slavio_set_irq(uint32_t target_cpu, int irq, uint32_t pil, int level) "Set cpu %d irq %d -> pil %d level %d"
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disable slavio_set_timer_irq_cpu(int cpu, int level) "Set cpu %d local timer level %d"
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# hw/slavio_misc.c
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disable slavio_misc_update_irq_raise(void) "Raise IRQ"
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disable slavio_misc_update_irq_lower(void) "Lower IRQ"
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disable slavio_set_power_fail(int power_failing, uint8_t config) "Power fail: %d, config: %d"
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disable slavio_cfg_mem_writeb(uint32_t val) "Write config %02x"
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disable slavio_cfg_mem_readb(uint32_t ret) "Read config %02x"
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disable slavio_diag_mem_writeb(uint32_t val) "Write diag %02x"
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disable slavio_diag_mem_readb(uint32_t ret) "Read diag %02x"
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disable slavio_mdm_mem_writeb(uint32_t val) "Write modem control %02x"
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disable slavio_mdm_mem_readb(uint32_t ret) "Read modem control %02x"
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disable slavio_aux1_mem_writeb(uint32_t val) "Write aux1 %02x"
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disable slavio_aux1_mem_readb(uint32_t ret) "Read aux1 %02x"
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disable slavio_aux2_mem_writeb(uint32_t val) "Write aux2 %02x"
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disable slavio_aux2_mem_readb(uint32_t ret) "Read aux2 %02x"
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disable apc_mem_writeb(uint32_t val) "Write power management %02x"
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disable apc_mem_readb(uint32_t ret) "Read power management %02x"
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disable slavio_sysctrl_mem_writel(uint32_t val) "Write system control %08x"
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disable slavio_sysctrl_mem_readl(uint32_t ret) "Read system control %08x"
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disable slavio_led_mem_writew(uint32_t val) "Write diagnostic LED %04x"
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disable slavio_led_mem_readw(uint32_t ret) "Read diagnostic LED %04x"
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# hw/slavio_timer.c
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disable slavio_timer_get_out(uint64_t limit, uint32_t counthigh, uint32_t count) "limit %"PRIx64" count %x%08x"
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disable slavio_timer_irq(uint32_t counthigh, uint32_t count) "callback: count %x%08x"
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disable slavio_timer_mem_readl_invalid(uint64_t addr) "invalid read address %"PRIx64""
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disable slavio_timer_mem_readl(uint64_t addr, uint32_t ret) "read %"PRIx64" = %08x"
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disable slavio_timer_mem_writel(uint64_t addr, uint32_t val) "write %"PRIx64" = %08x"
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disable slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer set to %016"PRIx64""
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disable slavio_timer_mem_writel_counter_invalid(void) "not user timer"
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disable slavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started"
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disable slavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped"
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disable slavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to user timer"
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disable slavio_timer_mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user timer to counter"
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disable slavio_timer_mem_writel_mode_invalid(void) "not system timer"
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disable slavio_timer_mem_writel_invalid(uint64_t addr) "invalid write address %"PRIx64""
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# hw/sparc32_dma.c
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disable ledma_memory_read(uint64_t addr) "DMA read addr 0x%"PRIx64""
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disable ledma_memory_write(uint64_t addr) "DMA write addr 0x%"PRIx64""
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disable sparc32_dma_set_irq_raise(void) "Raise IRQ"
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disable sparc32_dma_set_irq_lower(void) "Lower IRQ"
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disable espdma_memory_read(uint32_t addr) "DMA read addr 0x%08x"
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disable espdma_memory_write(uint32_t addr) "DMA write addr 0x%08x"
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disable sparc32_dma_mem_readl(uint64_t addr, uint32_t ret) "read dmareg %"PRIx64": 0x%08x"
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disable sparc32_dma_mem_writel(uint64_t addr, uint32_t old, uint32_t val) "write dmareg %"PRIx64": 0x%08x -> 0x%08x"
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disable sparc32_dma_enable_raise(void) "Raise DMA enable"
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disable sparc32_dma_enable_lower(void) "Lower DMA enable"
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# hw/sun4m.c
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disable sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d"
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disable sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d"
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disable sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d"
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disable sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d"
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# hw/sun4m_iommu.c
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disable sun4m_iommu_mem_readl(uint64_t addr, uint32_t ret) "read reg[%"PRIx64"] = %x"
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disable sun4m_iommu_mem_writel(uint64_t addr, uint32_t val) "write reg[%"PRIx64"] = %x"
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disable sun4m_iommu_mem_writel_ctrl(uint64_t iostart) "iostart = %"PRIx64""
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disable sun4m_iommu_mem_writel_tlbflush(uint32_t val) "tlb flush %x"
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disable sun4m_iommu_mem_writel_pgflush(uint32_t val) "page flush %x"
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disable sun4m_iommu_page_get_flags(uint64_t pa, uint64_t iopte, uint32_t ret) "get flags addr %"PRIx64" => pte %"PRIx64", *pte = %x"
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disable sun4m_iommu_translate_pa(uint64_t addr, uint64_t pa, uint32_t iopte) "xlate dva %"PRIx64" => pa %"PRIx64" iopte = %x"
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disable sun4m_iommu_bad_addr(uint64_t addr) "bad addr %"PRIx64""
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# hw/usb-desc.c
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disable usb_desc_device(int addr, int len, int ret) "dev %d query device, len %d, ret %d"
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disable usb_desc_device_qualifier(int addr, int len, int ret) "dev %d query device qualifier, len %d, ret %d"
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disable usb_desc_config(int addr, int index, int len, int ret) "dev %d query config %d, len %d, ret %d"
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disable usb_desc_other_speed_config(int addr, int index, int len, int ret) "dev %d query config %d, len %d, ret %d"
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disable usb_desc_string(int addr, int index, int len, int ret) "dev %d query string %d, len %d, ret %d"
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disable usb_set_addr(int addr) "dev %d"
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disable usb_set_config(int addr, int config, int ret) "dev %d, config %d, ret %d"
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disable usb_clear_device_feature(int addr, int feature, int ret) "dev %d, feature %d, ret %d"
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disable usb_set_device_feature(int addr, int feature, int ret) "dev %d, feature %d, ret %d"
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# vl.c
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disable vm_state_notify(int running, int reason) "running %d reason %d"
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# block/qed-l2-cache.c
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disable qed_alloc_l2_cache_entry(void *l2_cache, void *entry) "l2_cache %p entry %p"
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disable qed_unref_l2_cache_entry(void *entry, int ref) "entry %p ref %d"
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disable qed_find_l2_cache_entry(void *l2_cache, void *entry, uint64_t offset, int ref) "l2_cache %p entry %p offset %"PRIu64" ref %d"
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# block/qed-table.c
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disable qed_read_table(void *s, uint64_t offset, void *table) "s %p offset %"PRIu64" table %p"
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disable qed_read_table_cb(void *s, void *table, int ret) "s %p table %p ret %d"
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disable qed_write_table(void *s, uint64_t offset, void *table, unsigned int index, unsigned int n) "s %p offset %"PRIu64" table %p index %u n %u"
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disable qed_write_table_cb(void *s, void *table, int flush, int ret) "s %p table %p flush %d ret %d"
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# block/qed.c
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disable qed_aio_complete(void *s, void *acb, int ret) "s %p acb %p ret %d"
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disable qed_aio_setup(void *s, void *acb, int64_t sector_num, int nb_sectors, void *opaque, int is_write) "s %p acb %p sector_num %"PRId64" nb_sectors %d opaque %p is_write %d"
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disable qed_aio_next_io(void *s, void *acb, int ret, uint64_t cur_pos) "s %p acb %p ret %d cur_pos %"PRIu64""
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disable qed_aio_read_data(void *s, void *acb, int ret, uint64_t offset, size_t len) "s %p acb %p ret %d offset %"PRIu64" len %zu"
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disable qed_aio_write_data(void *s, void *acb, int ret, uint64_t offset, size_t len) "s %p acb %p ret %d offset %"PRIu64" len %zu"
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disable qed_aio_write_prefill(void *s, void *acb, uint64_t start, size_t len, uint64_t offset) "s %p acb %p start %"PRIu64" len %zu offset %"PRIu64""
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disable qed_aio_write_postfill(void *s, void *acb, uint64_t start, size_t len, uint64_t offset) "s %p acb %p start %"PRIu64" len %zu offset %"PRIu64""
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disable qed_aio_write_main(void *s, void *acb, int ret, uint64_t offset, size_t len) "s %p acb %p ret %d offset %"PRIu64" len %zu"
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# hw/grlib_gptimer.c
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disable grlib_gptimer_enable(int id, uint32_t count) "timer:%d set count 0x%x and run"
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disable grlib_gptimer_disabled(int id, uint32_t config) "timer:%d Timer disable config 0x%x"
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disable grlib_gptimer_restart(int id, uint32_t reload) "timer:%d reload val: 0x%x"
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disable grlib_gptimer_set_scaler(uint32_t scaler, uint32_t freq) "scaler:0x%x freq: 0x%x"
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disable grlib_gptimer_hit(int id) "timer:%d HIT"
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disable grlib_gptimer_readl(int id, const char *s, uint32_t val) "timer:%d %s 0x%x"
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disable grlib_gptimer_writel(int id, const char *s, uint32_t val) "timer:%d %s 0x%x"
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disable grlib_gptimer_unknown_register(const char *op, uint64_t val) "%s unknown register 0x%"PRIx64""
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# hw/grlib_irqmp.c
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disable grlib_irqmp_check_irqs(uint32_t pend, uint32_t force, uint32_t mask, uint32_t lvl1, uint32_t lvl2) "pend:0x%04x force:0x%04x mask:0x%04x lvl1:0x%04x lvl0:0x%04x\n"
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disable grlib_irqmp_ack(int intno) "interrupt:%d"
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disable grlib_irqmp_set_irq(int irq) "Raise CPU IRQ %d"
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disable grlib_irqmp_unknown_register(const char *op, uint64_t val) "%s unknown register 0x%"PRIx64""
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# hw/grlib_apbuart.c
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disable grlib_apbuart_event(int event) "event:%d"
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disable grlib_apbuart_unknown_register(const char *op, uint64_t val) "%s unknown register 0x%"PRIx64""
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# hw/leon3.c
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disable leon3_set_irq(int intno) "Set CPU IRQ %d"
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disable leon3_reset_irq(int intno) "Reset CPU IRQ %d"
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# spice-qemu-char.c
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disable spice_vmc_write(ssize_t out, int len) "spice wrottn %lu of requested %zd"
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disable spice_vmc_read(int bytes, int len) "spice read %lu of requested %zd"
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disable spice_vmc_register_interface(void *scd) "spice vmc registered interface %p"
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disable spice_vmc_unregister_interface(void *scd) "spice vmc unregistered interface %p"
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# hw/lm32_pic.c
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disable lm32_pic_raise_irq(void) "Raise CPU interrupt"
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disable lm32_pic_lower_irq(void) "Lower CPU interrupt"
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disable lm32_pic_interrupt(int irq, int level) "Set IRQ%d %d"
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disable lm32_pic_set_im(uint32_t im) "im 0x%08x"
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disable lm32_pic_set_ip(uint32_t ip) "ip 0x%08x"
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disable lm32_pic_get_im(uint32_t im) "im 0x%08x"
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disable lm32_pic_get_ip(uint32_t ip) "ip 0x%08x"
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# hw/lm32_juart.c
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disable lm32_juart_get_jtx(uint32_t value) "jtx 0x%08x"
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disable lm32_juart_set_jtx(uint32_t value) "jtx 0x%08x"
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disable lm32_juart_get_jrx(uint32_t value) "jrx 0x%08x"
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disable lm32_juart_set_jrx(uint32_t value) "jrx 0x%08x"
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# hw/lm32_timer.c
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disable lm32_timer_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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disable lm32_timer_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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disable lm32_timer_hit(void) "timer hit"
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disable lm32_timer_irq_state(int level) "irq state %d"
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# hw/lm32_uart.c
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disable lm32_uart_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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disable lm32_uart_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
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disable lm32_uart_irq_state(int level) "irq state %d"
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