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insn_trans
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Replace config-time define HOST_WORDS_BIGENDIAN
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2022-04-06 10:50:37 +02:00 |
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arch_dump.c
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target-riscv: support QMP dump-guest-memory
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2021-03-04 09:43:29 -05:00 |
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bitmanip_helper.c
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target/riscv: Add rev8 instruction, removing grev/grevi
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2021-10-07 08:41:33 +10:00 |
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cpu_bits.h
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target/riscv: add support for svpbmt extension
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2022-02-16 12:25:52 +10:00 |
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cpu_helper.c
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target/riscv: hardwire mstatus.FS to zero when enable zfinx
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2022-03-03 13:14:50 +10:00 |
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cpu_user.h
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Supply missing header guards
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2019-06-12 13:20:21 +02:00 |
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cpu-param.h
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target/riscv: Add a virtualised MMU Mode
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2020-11-09 15:08:45 -08:00 |
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cpu.c
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target/riscv: expose zfinx, zdinx, zhinx{min} properties
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2022-03-03 13:14:50 +10:00 |
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cpu.h
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Move CPU softfloat unions to cpu-float.h
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2022-04-06 14:31:43 +02:00 |
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csr.c
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target/riscv: Avoid leaking "no translation" TLB entries
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2022-04-01 08:40:42 +10:00 |
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fpu_helper.c
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target/riscv: add support for zhinx/zhinxmin
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2022-03-03 13:14:50 +10:00 |
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gdbstub.c
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target/riscv: correct "code should not be reached" for x-rv128
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2022-02-16 12:24:18 +10:00 |
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helper.h
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target/riscv: add support for zhinx/zhinxmin
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2022-03-03 13:14:50 +10:00 |
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insn16.decode
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target/riscv: accessors to registers upper part and 128-bit load/store
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2022-01-08 15:46:10 +10:00 |
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insn32.decode
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target/riscv: add support for svinval extension
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2022-02-16 12:25:52 +10:00 |
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instmap.h
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target/riscv: progressively load the instruction during decode
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2020-02-25 20:20:23 +00:00 |
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internals.h
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target/riscv: add support for zhinx/zhinxmin
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2022-03-03 13:14:50 +10:00 |
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Kconfig
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meson: Introduce target-specific Kconfig
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2021-07-09 18:21:34 +02:00 |
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kvm_riscv.h
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target/riscv: Support setting external interrupt by KVM
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2022-01-21 15:52:56 +10:00 |
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kvm-stub.c
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target/riscv: Support setting external interrupt by KVM
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2022-01-21 15:52:56 +10:00 |
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kvm.c
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Remove qemu-common.h include from most units
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2022-04-06 14:31:55 +02:00 |
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m128_helper.c
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target/riscv: support for 128-bit M extension
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2022-01-08 15:46:10 +10:00 |
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machine.c
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target/riscv: Implement AIA xiselect and xireg CSRs
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2022-02-16 12:24:19 +10:00 |
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meson.build
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target/riscv: Add XVentanaCondOps custom extension
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2022-02-16 12:24:18 +10:00 |
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monitor.c
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target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
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2021-10-22 07:47:51 +10:00 |
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op_helper.c
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target/riscv: Adjust csr write mask with XLEN
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2022-01-21 15:52:57 +10:00 |
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pmp.c
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target/riscv: Adjust pmpcfg access with mxl
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2022-01-21 15:52:57 +10:00 |
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pmp.h
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target: Include missing 'cpu.h'
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2022-03-06 13:15:42 +01:00 |
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sbi_ecall_interface.h
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target/riscv: Handle KVM_EXIT_RISCV_SBI exit
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2022-01-21 15:52:56 +10:00 |
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trace-events
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target/riscv: Add ePMP CSR access functions
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2021-05-11 20:02:06 +10:00 |
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trace.h
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trace: switch position of headers to what Meson requires
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2020-08-21 06:18:24 -04:00 |
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translate.c
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target/riscv: add support for zdinx
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2022-03-03 13:14:50 +10:00 |
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vector_helper.c
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Replace config-time define HOST_WORDS_BIGENDIAN
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2022-04-06 10:50:37 +02:00 |
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XVentanaCondOps.decode
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target/riscv: Add XVentanaCondOps custom extension
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2022-02-16 12:24:18 +10:00 |
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