Marc-André Lureau e03b56863d Replace config-time define HOST_WORDS_BIGENDIAN ... Replace a config-time define with a compile time condition define (compatible with clang and gcc) that must be declared prior to its usage. This avoids having a global configure time define, but also prevents from bad usage, if the config header wasn't included before. This can help to make some code independent from qemu too. gcc supports __BYTE_ORDER__ from about 4.6 and clang from 3.2. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> [ For the s390x parts I'm involved in ] Acked-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323155743.1585078-7-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2022-04-06 10:50:37 +02:00
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trans_privileged.c.inc	target/riscv: Sign extend pc for different XLEN	2022-01-21 15:52:57 +10:00
trans_rva.c.inc	target/riscv: Calculate address according to XLEN	2022-01-21 15:52:57 +10:00
trans_rvb.c.inc	target/riscv: fix inverted checks for ext_zb[abcs]	2022-03-03 13:14:50 +10:00
trans_rvd.c.inc	target/riscv: add support for zdinx	2022-03-03 13:14:50 +10:00
trans_rvf.c.inc	target/riscv: add support for zfinx	2022-03-03 13:14:50 +10:00
trans_rvh.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvi.c.inc	target/riscv: access configuration through cfg_ptr in DisasContext	2022-02-16 12:24:18 +10:00
trans_rvm.c.inc	target/riscv: support for 128-bit M extension	2022-01-08 15:46:10 +10:00
trans_rvv.c.inc	Replace config-time define HOST_WORDS_BIGENDIAN	2022-04-06 10:50:37 +02:00
trans_rvzfh.c.inc	target/riscv: add support for zhinx/zhinxmin	2022-03-03 13:14:50 +10:00
trans_svinval.c.inc	target/riscv: add support for svinval extension	2022-02-16 12:25:52 +10:00
trans_xventanacondops.c.inc	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00