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This relatively small architectural feature adds the following: FIR.FREP: Read-only. If FREP=1, then Config5.FRE and Config5.UFE are available. Config5.FRE: When enabled all single-precision FP arithmetic instructions, LWC1/LWXC1/MTC1, SWC1/SWXC1/MFC1 cause a Reserved Instructions exception. Config5.UFE: Allows user to write/read Config5.FRE using CTC1/CFC1 instructions. Enable the feature in MIPS64R6-generic CPU. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> |
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.. | ||
cpu-qom.h | ||
cpu.c | ||
cpu.h | ||
dsp_helper.c | ||
gdbstub.c | ||
helper.c | ||
helper.h | ||
kvm_mips.h | ||
kvm.c | ||
lmi_helper.c | ||
machine.c | ||
Makefile.objs | ||
mips-defs.h | ||
msa_helper.c | ||
op_helper.c | ||
TODO | ||
translate_init.c | ||
translate.c |