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xemu/target-tricore
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Bastian Koppelmann 9655b9328a target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode 
Add instructions of RR1 opcode format, that have 0xb3 as first opcode.
Add helper functions mulh, mulmh and mulrh, that compute multiplication,
with multiprecision (mulmh) or rounding (mulrh) of 4 halfwords, being either low or high parts
of two 32 bit regs.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21 18:35:49 +00:00
..
cpu-qom.h target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
cpu.c target-tricore: Make TRICORE_FEATURES implying others. 2014-12-10 11:13:45 +00:00
cpu.h target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
csfr.def target-tricore: Add instructions of RLC opcode format 2014-12-10 11:13:45 +00:00
helper.c target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
helper.h target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode 2014-12-21 18:35:49 +00:00
Makefile.objs target-tricore: Add target stubs and qom-cpu 2014-09-01 14:49:20 +01:00
op_helper.c target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode 2014-12-21 18:35:49 +00:00
translate.c target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode 2014-12-21 18:35:49 +00:00
tricore-defs.h target-tricore: Add target stubs and qom-cpu 2014-09-01 14:49:20 +01:00
tricore-opcodes.h target-tricore: Fix MFCR/MTCR insn and B format offset. 2014-12-21 18:35:38 +00:00