Maciej W. Rozycki 800675f117 target-mips: Correct the handling of register #72 on writes ...

Fix an off-by-one error in `mips_cpu_gdb_write_register' for register
matching how `mips_cpu_gdb_read_register' handles it.  This register
slot is a fake anyway, there's nothing in hardware that corresponds to
it.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>

2014-12-16 12:45:19 +00:00

..

cpu-qom.h

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cpu.c

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cpu.h

mips: Add macros for CP0.Config3 and CP0.Config4 bits

2014-11-07 14:15:28 +00:00

dsp_helper.c

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gdbstub.c

target-mips: Correct the handling of register #72 on writes

2014-12-16 12:45:19 +00:00

helper.c

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helper.h

target-mips: add MSA MI10 format instructions

2014-11-03 11:48:35 +00:00

kvm_mips.h

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kvm.c

target-mips: kvm: do not use get_clock()

2014-12-15 12:21:01 +01:00

lmi_helper.c

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machine.c

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Makefile.objs

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mips-defs.h

…

msa_helper.c

target-mips: add MSA 2RF format instructions

2014-11-03 11:48:35 +00:00

op_helper.c

target-mips: add MSA MI10 format instructions

2014-11-03 11:48:35 +00:00

TODO

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translate_init.c

mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

2014-11-07 14:15:28 +00:00

translate.c

target-mips: fix multiple TCG registers covering same data

2014-11-07 14:15:28 +00:00