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8217606e6e
Add the parameter 'order' to qemu_register_reset and sort callbacks on registration. On system reset, callbacks with lower order will be invoked before those with higher order. Update all existing users to the standard order 0. Note: At least for x86, the existing users seem to assume that handlers are called in their registration order. Therefore, the patch preserves this property. If someone feels bored, (s)he could try to identify this dependency and express it properly on callback registration. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
273 lines
9.1 KiB
C
273 lines
9.1 KiB
C
/*
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* QEMU Uninorth PCI host (for all Mac99 and newer machines)
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "ppc_mac.h"
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#include "pci.h"
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/* debug UniNorth */
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//#define DEBUG_UNIN
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#ifdef DEBUG_UNIN
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#define UNIN_DPRINTF(fmt, ...) \
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do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define UNIN_DPRINTF(fmt, ...)
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#endif
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typedef target_phys_addr_t pci_addr_t;
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#include "pci_host.h"
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typedef PCIHostState UNINState;
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static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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UNINState *s = opaque;
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UNIN_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr, val);
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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s->config_reg = val;
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}
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static uint32_t pci_unin_main_config_readl (void *opaque,
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target_phys_addr_t addr)
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{
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UNINState *s = opaque;
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uint32_t val;
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val = s->config_reg;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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UNIN_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr, val);
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return val;
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}
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static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
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&pci_unin_main_config_writel,
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&pci_unin_main_config_writel,
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&pci_unin_main_config_writel,
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};
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static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
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&pci_unin_main_config_readl,
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&pci_unin_main_config_readl,
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&pci_unin_main_config_readl,
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};
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static CPUWriteMemoryFunc *pci_unin_main_write[] = {
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&pci_host_data_writeb,
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&pci_host_data_writew,
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&pci_host_data_writel,
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};
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static CPUReadMemoryFunc *pci_unin_main_read[] = {
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&pci_host_data_readb,
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&pci_host_data_readw,
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&pci_host_data_readl,
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};
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static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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UNINState *s = opaque;
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s->config_reg = val;
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}
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static uint32_t pci_unin_config_readl (void *opaque,
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target_phys_addr_t addr)
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{
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UNINState *s = opaque;
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return s->config_reg;
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}
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static CPUWriteMemoryFunc *pci_unin_config_write[] = {
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&pci_unin_config_writel,
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&pci_unin_config_writel,
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&pci_unin_config_writel,
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};
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static CPUReadMemoryFunc *pci_unin_config_read[] = {
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&pci_unin_config_readl,
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&pci_unin_config_readl,
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&pci_unin_config_readl,
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};
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#if 0
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static CPUWriteMemoryFunc *pci_unin_write[] = {
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&pci_host_pci_writeb,
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&pci_host_pci_writew,
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&pci_host_pci_writel,
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};
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static CPUReadMemoryFunc *pci_unin_read[] = {
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&pci_host_pci_readb,
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&pci_host_pci_readw,
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&pci_host_pci_readl,
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};
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#endif
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/* Don't know if this matches real hardware, but it agrees with OHW. */
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static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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return (irq_num + (pci_dev->devfn >> 3)) & 3;
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}
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static void pci_unin_set_irq(qemu_irq *pic, int irq_num, int level)
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{
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qemu_set_irq(pic[irq_num + 8], level);
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}
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static void pci_unin_save(QEMUFile* f, void *opaque)
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{
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PCIDevice *d = opaque;
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pci_device_save(d, f);
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}
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static int pci_unin_load(QEMUFile* f, void *opaque, int version_id)
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{
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PCIDevice *d = opaque;
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if (version_id != 1)
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return -EINVAL;
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return pci_device_load(d, f);
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}
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static void pci_unin_reset(void *opaque)
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{
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}
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PCIBus *pci_pmac_init(qemu_irq *pic)
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{
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UNINState *s;
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PCIDevice *d;
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int pci_mem_config, pci_mem_data;
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/* Use values found on a real PowerMac */
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/* Uninorth main bus */
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s = qemu_mallocz(sizeof(UNINState));
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s->bus = pci_register_bus(pci_unin_set_irq, pci_unin_map_irq,
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pic, 11 << 3, 4);
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pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
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pci_unin_main_config_write, s);
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pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
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pci_unin_main_write, s);
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cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config);
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cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data);
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d = pci_register_device(s->bus, "Uni-north main", sizeof(PCIDevice),
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11 << 3, NULL, NULL);
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pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
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pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
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d->config[0x08] = 0x00; // revision
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pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
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d->config[0x0C] = 0x08; // cache_line_size
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d->config[0x0D] = 0x10; // latency_timer
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d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
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d->config[0x34] = 0x00; // capabilities_pointer
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#if 0 // XXX: not activated as PPC BIOS doesn't handle multiple buses properly
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/* pci-to-pci bridge */
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d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
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NULL, NULL);
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pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
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pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
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d->config[0x08] = 0x05; // revision
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pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
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d->config[0x0C] = 0x08; // cache_line_size
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d->config[0x0D] = 0x20; // latency_timer
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d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
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d->config[0x18] = 0x01; // primary_bus
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d->config[0x19] = 0x02; // secondary_bus
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d->config[0x1A] = 0x02; // subordinate_bus
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d->config[0x1B] = 0x20; // secondary_latency_timer
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d->config[0x1C] = 0x11; // io_base
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d->config[0x1D] = 0x01; // io_limit
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d->config[0x20] = 0x00; // memory_base
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d->config[0x21] = 0x80;
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d->config[0x22] = 0x00; // memory_limit
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d->config[0x23] = 0x80;
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d->config[0x24] = 0x01; // prefetchable_memory_base
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d->config[0x25] = 0x80;
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d->config[0x26] = 0xF1; // prefectchable_memory_limit
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d->config[0x27] = 0x7F;
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// d->config[0x34] = 0xdc // capabilities_pointer
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#endif
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/* Uninorth AGP bus */
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pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
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pci_unin_config_write, s);
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pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
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pci_unin_main_write, s);
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cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
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cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);
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d = pci_register_device(s->bus, "Uni-north AGP", sizeof(PCIDevice),
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11 << 3, NULL, NULL);
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pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
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pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
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d->config[0x08] = 0x00; // revision
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pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
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d->config[0x0C] = 0x08; // cache_line_size
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d->config[0x0D] = 0x10; // latency_timer
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d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
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// d->config[0x34] = 0x80; // capabilities_pointer
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#if 0 // XXX: not needed for now
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/* Uninorth internal bus */
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s = &pci_bridge[2];
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pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
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pci_unin_config_write, s);
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pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
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pci_unin_write, s);
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cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
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cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
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d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
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3, 11 << 3, NULL, NULL);
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pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
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pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
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d->config[0x08] = 0x00; // revision
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pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
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d->config[0x0C] = 0x08; // cache_line_size
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d->config[0x0D] = 0x10; // latency_timer
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d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
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d->config[0x34] = 0x00; // capabilities_pointer
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#endif
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register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, d);
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qemu_register_reset(pci_unin_reset, 0, d);
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pci_unin_reset(d);
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return s->bus;
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}
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