Cédric Le Goater 8256870ada ppc/xive: Make the PIPR register readonly
When the hypervisor (KVM) dispatches a vCPU on a HW thread, it restores
its thread interrupt context. The Pending Interrupt Priority Register
(PIPR) is computed from the Interrupt Pending Buffer (IPB) and stores
should not be allowed to change its value.

Fixes: 207d9fe98510 ("ppc/xive: introduce the XIVE interrupt thread context")
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190630204601.30574-3-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-07-02 09:43:58 +10:00
..
2019-06-24 10:42:30 +01:00
2019-06-16 16:16:52 -04:00
2019-07-01 13:03:51 +01:00
2019-06-24 10:42:30 +01:00
2019-06-24 10:42:30 +01:00
2019-06-26 13:25:07 +02:00
2019-06-12 13:20:21 +02:00
2019-06-12 13:20:21 +02:00
2019-06-24 10:42:30 +01:00
2019-06-16 16:16:52 -04:00
2019-06-21 13:25:29 +02:00
2019-06-24 10:42:30 +01:00
2019-06-24 10:42:30 +01:00