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6efbac908f
There is not much differences with the A0 revision apart from the DDR calibration. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-10-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
284 lines
8.4 KiB
C
284 lines
8.4 KiB
C
/*
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* ASPEED SDRAM Memory Controller
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*
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* Copyright (C) 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "hw/misc/aspeed_sdmc.h"
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#include "hw/misc/aspeed_scu.h"
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
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#include "trace.h"
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/* Protection Key Register */
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#define R_PROT (0x00 / 4)
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#define PROT_KEY_UNLOCK 0xFC600309
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/* Configuration Register */
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#define R_CONF (0x04 / 4)
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/*
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* Configuration register Ox4 (for Aspeed AST2400 SOC)
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*
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* These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is
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* what we care about right now as it is checked by U-Boot to
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* determine the RAM size.
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*/
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#define ASPEED_SDMC_RESERVED 0xFFFFF800 /* 31:11 reserved */
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#define ASPEED_SDMC_AST2300_COMPAT (1 << 10)
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#define ASPEED_SDMC_SCRAMBLE_PATTERN (1 << 9)
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#define ASPEED_SDMC_DATA_SCRAMBLE (1 << 8)
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#define ASPEED_SDMC_ECC_ENABLE (1 << 7)
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#define ASPEED_SDMC_VGA_COMPAT (1 << 6) /* readonly */
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#define ASPEED_SDMC_DRAM_BANK (1 << 5)
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#define ASPEED_SDMC_DRAM_BURST (1 << 4)
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#define ASPEED_SDMC_VGA_APERTURE(x) ((x & 0x3) << 2) /* readonly */
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#define ASPEED_SDMC_VGA_8MB 0x0
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#define ASPEED_SDMC_VGA_16MB 0x1
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#define ASPEED_SDMC_VGA_32MB 0x2
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#define ASPEED_SDMC_VGA_64MB 0x3
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#define ASPEED_SDMC_DRAM_SIZE(x) (x & 0x3)
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#define ASPEED_SDMC_DRAM_64MB 0x0
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#define ASPEED_SDMC_DRAM_128MB 0x1
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#define ASPEED_SDMC_DRAM_256MB 0x2
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#define ASPEED_SDMC_DRAM_512MB 0x3
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#define ASPEED_SDMC_READONLY_MASK \
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(ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT | \
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ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
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/*
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* Configuration register Ox4 (for Aspeed AST2500 SOC and higher)
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*
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* Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION
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* should be set to 1 for the AST2500 SOC.
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*/
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#define ASPEED_SDMC_HW_VERSION(x) ((x & 0xf) << 28) /* readonly */
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#define ASPEED_SDMC_SW_VERSION ((x & 0xff) << 20)
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#define ASPEED_SDMC_CACHE_INITIAL_DONE (1 << 19) /* readonly */
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#define ASPEED_SDMC_AST2500_RESERVED 0x7C000 /* 18:14 reserved */
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#define ASPEED_SDMC_CACHE_DDR4_CONF (1 << 13)
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#define ASPEED_SDMC_CACHE_INITIAL (1 << 12)
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#define ASPEED_SDMC_CACHE_RANGE_CTRL (1 << 11)
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#define ASPEED_SDMC_CACHE_ENABLE (1 << 10) /* differs from AST2400 */
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#define ASPEED_SDMC_DRAM_TYPE (1 << 4) /* differs from AST2400 */
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/* DRAM size definitions differs */
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#define ASPEED_SDMC_AST2500_128MB 0x0
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#define ASPEED_SDMC_AST2500_256MB 0x1
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#define ASPEED_SDMC_AST2500_512MB 0x2
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#define ASPEED_SDMC_AST2500_1024MB 0x3
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#define ASPEED_SDMC_AST2500_READONLY_MASK \
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(ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \
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ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \
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ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
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static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)
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{
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AspeedSDMCState *s = ASPEED_SDMC(opaque);
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addr >>= 2;
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if (addr >= ARRAY_SIZE(s->regs)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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return 0;
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}
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return s->regs[addr];
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}
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static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned int size)
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{
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AspeedSDMCState *s = ASPEED_SDMC(opaque);
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addr >>= 2;
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if (addr >= ARRAY_SIZE(s->regs)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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return;
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}
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if (addr != R_PROT && s->regs[R_PROT] != PROT_KEY_UNLOCK) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
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return;
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}
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if (addr == R_CONF) {
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/* Make sure readonly bits are kept */
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switch (s->silicon_rev) {
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case AST2400_A0_SILICON_REV:
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case AST2400_A1_SILICON_REV:
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data &= ~ASPEED_SDMC_READONLY_MASK;
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break;
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case AST2500_A0_SILICON_REV:
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data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
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break;
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default:
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g_assert_not_reached();
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}
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}
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s->regs[addr] = data;
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}
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static const MemoryRegionOps aspeed_sdmc_ops = {
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.read = aspeed_sdmc_read,
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.write = aspeed_sdmc_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static int ast2400_rambits(AspeedSDMCState *s)
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{
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switch (s->ram_size >> 20) {
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case 64:
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return ASPEED_SDMC_DRAM_64MB;
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case 128:
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return ASPEED_SDMC_DRAM_128MB;
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case 256:
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return ASPEED_SDMC_DRAM_256MB;
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case 512:
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return ASPEED_SDMC_DRAM_512MB;
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default:
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break;
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}
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/* use a common default */
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error_report("warning: Invalid RAM size 0x%" PRIx64
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". Using default 256M", s->ram_size);
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s->ram_size = 256 << 20;
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return ASPEED_SDMC_DRAM_256MB;
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}
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static int ast2500_rambits(AspeedSDMCState *s)
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{
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switch (s->ram_size >> 20) {
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case 128:
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return ASPEED_SDMC_AST2500_128MB;
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case 256:
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return ASPEED_SDMC_AST2500_256MB;
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case 512:
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return ASPEED_SDMC_AST2500_512MB;
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case 1024:
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return ASPEED_SDMC_AST2500_1024MB;
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default:
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break;
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}
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/* use a common default */
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error_report("warning: Invalid RAM size 0x%" PRIx64
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". Using default 512M", s->ram_size);
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s->ram_size = 512 << 20;
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return ASPEED_SDMC_AST2500_512MB;
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}
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static void aspeed_sdmc_reset(DeviceState *dev)
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{
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AspeedSDMCState *s = ASPEED_SDMC(dev);
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memset(s->regs, 0, sizeof(s->regs));
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/* Set ram size bit and defaults values */
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switch (s->silicon_rev) {
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case AST2400_A0_SILICON_REV:
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case AST2400_A1_SILICON_REV:
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s->regs[R_CONF] |=
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ASPEED_SDMC_VGA_COMPAT |
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ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
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break;
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case AST2500_A0_SILICON_REV:
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case AST2500_A1_SILICON_REV:
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s->regs[R_CONF] |=
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ASPEED_SDMC_HW_VERSION(1) |
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ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
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ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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AspeedSDMCState *s = ASPEED_SDMC(dev);
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if (!is_supported_silicon_rev(s->silicon_rev)) {
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error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
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s->silicon_rev);
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return;
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}
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switch (s->silicon_rev) {
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case AST2400_A0_SILICON_REV:
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case AST2400_A1_SILICON_REV:
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s->ram_bits = ast2400_rambits(s);
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break;
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case AST2500_A0_SILICON_REV:
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case AST2500_A1_SILICON_REV:
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s->ram_bits = ast2500_rambits(s);
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break;
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default:
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g_assert_not_reached();
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}
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memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,
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TYPE_ASPEED_SDMC, 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static const VMStateDescription vmstate_aspeed_sdmc = {
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.name = "aspeed.sdmc",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property aspeed_sdmc_properties[] = {
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DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0),
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DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void aspeed_sdmc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = aspeed_sdmc_realize;
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dc->reset = aspeed_sdmc_reset;
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dc->desc = "ASPEED SDRAM Memory Controller";
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dc->vmsd = &vmstate_aspeed_sdmc;
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dc->props = aspeed_sdmc_properties;
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}
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static const TypeInfo aspeed_sdmc_info = {
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.name = TYPE_ASPEED_SDMC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AspeedSDMCState),
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.class_init = aspeed_sdmc_class_init,
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};
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static void aspeed_sdmc_register_types(void)
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{
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type_register_static(&aspeed_sdmc_info);
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}
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type_init(aspeed_sdmc_register_types);
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